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TL16C752BTPTREP датащи(PDF) 11 Page - Texas Instruments

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номер детали TL16C752BTPTREP
подробное описание детали  3.3-V DUAL UART WITH 64-BYTE FIFO
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производитель  TI [Texas Instruments]
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TL16C752BTPTREP датащи(HTML) 11 Page - Texas Instruments

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TL16C752B-EP
3.3-V DUAL UART WITH 64-BYTE FIFO
SGLS153 – FEBRUARY 2003
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional description (continued)
polled mode operation
In polled mode (IER[3:0]=0000) the status of the receiver and transmitter can be checked by polling the line
status register (LSR). This mode is an alternative to the FIFO interrupt mode of operation where the status of
the receiver and transmitter is automatically known by means of interrupts sent to the CPU. Figure 6 shows FIFO
polled mode operation.
0
0
0
0
LSR
IER
THR
RHR
IOW/IOR
Processor
Figure 6. FIFO Polled Mode Operation
DMA signalling
There are two modes of DMA operation: DMA mode 0 or 1, selected by FCR[3].
In DMA mode 0 or FIFO disable (FCR[0]=0) DMA occurs in single character transfers. In DMA mode 1 multi-
character (or block) DMA transfers are managed to relieve the processor for longer periods of time.
single DMA transfers (DMA mode0/FIFO disable)
Transmitter: When empty, the TXRDY signal becomes active. TXRDY goes inactive after one character has
been loaded into it.
Receiver: RXRDY is active when there is at least one character in the FIFO. It becomes inactive when the
receiver is empty.
Figure 7 shows TXRDY and RXRDY in DMA mode0/FIFO disable.
FIFO Empty
TXRDY
wrptr
TXRDY
wrptr
At Least One
Location Filled
TX
FIFO Empty
RXRDY
rdptr
RXRDY
rdptr
At Least One
Location Filled
RX
Figure 7. TXRDY and RXRDY in DMA Mode 0/FIFO Disable


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