12-Bit, 170/210/250 MSPS

1.8 V A/D Converter

Preliminary Technical Data

AD9230

Rev. PrE

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FEATURES

Excellent Linearity

DNL = ±0.3 LSB (Typical)

INL = ±0.5 LSB (Typical)

LVDS at 250 MSPS (ANSI-644 levels)

900 MHz Full Power Analog Bandwidth

On-Chip Reference and Track-and-Hold

Power Dissipation = 425 mW Typical @ 250 MSPS

1.25 V Input Voltage Range

1.8 V Analog Supply Operation

Output Data Format Option

Data Clock Output Provided

Clock Duty Cycle Stabilizer

APPLICATIONS

Wireless and Wired Broadband Communications

Cable Reverse Path

Communications Test Equipment

Radar and Satellite Subsystems

Power Amplifier Linearization

PRODUCT DESCRIPTION

The AD9230 is a 12-bit monolithic sampling analog-to-digital

converter optimized for high performance, low power, and ease

of use. The product operates up to a 250 MSPS conversion rate

and is optimized for outstanding dynamic performance in

wideband carrier and broadband systems. All necessary

functions, including a track-and-hold (T/H) and voltage

reference, are included on the chip to provide a complete signal

conversion solution.

The ADC requires a 1.8 V analog voltage supply and a

differential clock for full performance operation. The digital

outputs are LVDS (ANSI-644) compatible and support either

twos complement, offset binary format or gray code. A data

clock output is available for proper output data timing.

12

Output

Staging -

LVDS

D11-D0

DCO-

DCO+

AVDD

(1.8V)

DrVDD

OTR+

12

Ref

ADC

12-bit

Core

T/H

Clock

Mgmt

CLK+

CLK-

SCLK

CSB

DGND

(Pin 0)

AGND

VIN+

VIN-

SDIO

Serial Port

OTR-

RESET

Figure 1. Functional Block Diagram

Fabricated on an advanced CMOS process, the AD9230 is

available in a 56-lead chip scale package (56 LFCSP) specified

over the industrial temperature range (–40°C to +85°C).

PRODUCT HIGHLIGHTS

1.

High Performance—Maintains 65.5 dB SNR @ 250 MSPS

with a 65 MHz input.

2.

Low Power—Consumes only 425 mW @ 250 MSPS.

3.

Ease of Use—LVDS output data and output clock signal

allow interface to current FPGA technology. The on-chip

reference and sample/hold provide flexibility in system

design. Use of a single 1.8 V supply simplifies system

power supply design. Supported DDR mode reduces

number of output data traces

4.

Serial Port Control - Standard serial port interface

supports various product functions such as data

formatting, enabling a clock duty cycle stabilizer, power

down, gain adjust and output test pattern generation.

5.

Pin compatible family – 10-bit pin compatible family

offered as AD9211.