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FM20L08-60-TG датащит (Datasheet) 9 Page - List of Unclassifed Manufacturers

№ деталь FM20L08-60-TG
подробность  1Mbit Bytewide FRAM Memory - Extended Temp
скачать  14 Pages
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производитель  ETC1 [List of Unclassifed Manufacturers]
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FM20L08 - Extended Temp.
Rev. 1.4
Oct. 2005
Page 9 of 14
Read Cycle AC Parameters (TA = -25
° C to +85° C, C
L = 30 pF, VDD = 3.3V +10%, -5% unless otherwise specified)
-60
Symbol
Parameter
Min
Max
Units
Notes
tRC
Read Cycle Time
350
-
ns
tCE
Chip Enable Access Time
-
60
ns
tAA
Address Access Time
-
350
ns
tOH
Output Hold Time
50
-
ns
tAAP
Page Mode Address Access Time
-
25
ns
tOHP
Page Mode Output Hold Time
5
-
ns
tCA
Chip Enable Active Time
60
-
ns
tPC
Precharge Time
290
-
ns
tAS
Address Setup Time (to /CE low)
5
-
ns
tAH
Address Hold Time (/CE-controlled)
60
-
ns
tOE
Output Enable Access Time
-
10
ns
tHZ
Chip Enable to Output High-Z
-
15
ns
1
tOHZ
Output Enable High to Output High-Z
-
15
ns
1
Write Cycle AC Parameters (TA = -25
° C to +85° C, V
DD = 3.3V +10%, -5% unless otherwise specified)
-60
Symbol
Parameter
Min
Max
Units
Notes
tWC
Write Cycle Time
350
-
ns
tCA
Chip Enable Active Time
60
-
ns
tCW
Chip Enable to Write Enable High
60
-
ns
tPC
Precharge Time
290
-
ns
tPWC
Page Mode Write Enable Cycle Time
30
-
ns
tWP
Write Enable Pulse Width
15
-
ns
tAS
Address Setup Time (to /CE low)
5
-
ns
tAH
Address Hold Time (/CE-controlled)
60
-
ns
tASP
Page Mode Address Setup Time (to /WE low)
5
-
ns
tAHP
Page Mode Address Hold Time (to /WE low)
15
-
ns
tWLC
Write Enable Low to /CE High
25
-
ns
tWLA
Write Enable Low to A(16:3) Change
25
-
ns
tAWH
A(16:3) Change to Write Enable High
350
-
ns
tDS
Data Input Setup Time
20
-
ns
tDH
Data Input Hold Time
0
-
ns
tWZ
Write Enable Low to Output High Z
-
15
ns
1
tWX
Write Enable High to Output Driven
5
-
ns
1
tWS
Write Enable to /CE Low Setup Time
0
-
ns
2
tWH
Write Enable to /CE High Hold Time
0
-
ns
2
Notes
1
This parameter is characterized but not 100% tested.
2
The relationship between /CE and /WE determines if a /CE- or /WE-controlled write occurs.
Power Cycle Timing (TA = -25
° C to +85° C, V
DD = 3.3V +10%, -5% unless otherwise specified)
Symbol
Parameter
Min
Max
Units
Notes
tPULV
Power Up to /LVL Inactive Time (VTP to /LVL high)
0
50
µs
tPDLV
Power Down to /LVL Active Time (VTP to /LVL low)
0
15
µs
tPU
Power Up (/LVL high) to First Access Time
0
-
µs
tPD
Last Access (/CE high) to Power Down (VDD min)
0
-
µs
tVR
VDD Rise Time
50
-
µs/V
1, 2
tVF
VDD Fall Time
100
-
µs/V
1, 2
Notes
1
Slope measured at any point on VDD waveform.




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