VMX51C900
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page 9 of 55
The SP’s default value at reset is 07h. The SP can be
programmed to point anywhere in the 00h to FFh RAM
memory range.
Each time a function call is performed or an interrupt is
serviced, the 16-bit return address (2 bytes) is stored
onto the stack. Data can also be placed manually on
the stack by using the PUSH and POP instructions.
Description of Power Control Register
The VMX51C900 provides two power saving modes:
Idle and Power Down, which are controlled by the
PDOWN and IDLE bits of the PCON register at
address 87h.
TABLE 9: POWER CONTROL REGISTER (PCON) - SFR 87H
7
6:4
3
2
1
0
SMOD
GF1
GF0
PDOWN
IDLE
Bit
Mnemonic
Description
7
SMOD
1: Double the baud rate of the serial port
frequency that was generated by Timer 1.
0: Normal serial port baud rate generated by
Timer 1.
6
5
4
3
GF1
General Purpose Flag
2
GF0
General Purpose Flag
1
PDOWN
Power Down mode control bit
0
IDLE
Idle mode control bit
The Idle mode is useful in applications that require
reduced power consumption. When in Idle mode, the
processor clock is stopped, but the peripherals
continue running. The contents of the RAM, I/O state
and SFR registers are maintained and the timer,
external interrupts and UARTs are left operational.
Since only the processor clock stops, normal operating
power will be cut to about half.
The processor will
awaken if an external event triggering an interrupt
occurs.
In Power Down mode, the VMX51C900 oscillator and
peripherals,
including
the
watchdog
timer,
are
disabled.
The contents of the RAM and the SFR
registers, however, are maintained.
When in Power Down mode, the VMX51C900 current
consumption drops to about 100uA. The only way to
exit a Power Down mode is to perform a hardware
reset.
The SMOD bit of the PCON register controls the
oscillator divisor applied to Timer1 when used as a
baud rate generator for the UART. Setting this bit to 1
doubles the frequency of the UART’s baud rate
generator.
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