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MC13001XP датащи(PDF) 5 Page - Motorola, Inc

номер детали MC13001XP
подробное описание детали  Monomax Black and White TV Subsystem
Download  10 Pages
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производитель  MOTOROLA [Motorola, Inc]
домашняя страница  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

MC13001XP датащи(HTML) 5 Page - Motorola, Inc

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MC13001X MC13007X
5
MOTOROLA ANALOG IC DEVICE DATA
The composite sync is stripped from a delayed and filtered
video in a peak detecting type of sync separator. The
components connected to Pin 7 determine the slice and tilt
levels of the sync separator. For ideal horizontal sync
separation and to ensure correct operating of AGC anti–
lockup circuit, a relatively short time constant is required at
Pin 7. This time constant is less than optimum for good noise
free vertical separation, giving rise to a vertical slice level
near sync tip. An additional longer time–constant is therefore
coupled to the first via a diode. With the correct choice of time
constants, the diode is non–conducting during the horizontal
sync period, but conducts during the longer vertical period.
This connects the longer time constant to the sync separator
for the vertical period and stops the slice level from moving up
the sync tip. The separated composite sync is integrated
internally, and the time constant is such that only the longer
period vertical pulses produce a significant output pulse. The
output is then fed to the vertical sync separator, which further
processes the vertical pulse and provides increased noise
protection. The selection of the external components
connected to the vertical separator at Pin 23 permits a wide
range of performance options. A simple resistor divider from
the 8.2 V regulated supply gives adequate performance for
most conditions. The addition of an RC network will make the
slice level adapt to varying sync amplitude and give improved
weak signal performance. A resistor to the AGC voltage on
Pin 9 enables the sync slice level to be changed as a function
of signal level. This further improves the low signal level
separation while at the same time giving increased impulse
noise protection on strong signals.
Horizontal Oscillator
The horizontal PLL (see Figure 7) is a two–loop system
using a 31.5 kHz oscillator which after a divider stage is
locked to the sync pulse using Phase Detector 1. The control
signal derived from this phase detector on Pin 13 is fed via a
high–value resistor to the frequency–control point on Pin 12.
The same divided oscillator frequency is also fed to Phase
Detector 2, where the flyback pulse is compared with it and
the resulting error used to change a variable slice level on the
oscillator ramp waveform. This therefore changes the timing
of the output square wave from the slicer and hence the
timing of the buffered horizontal output on Pin 17 (see
Figure 8). The error on Phase Detector 2 is reduced until the
phasing of the flyback pulse is correct with respect to the
divided oscillator waveform, and hence with respect to the
sync pulse.
15
13
7
17
200 mVpp
50 mVpp
4.5 V
6.0 V
2.0 V
0 V
+0.9 V
0 V
–0.7 V
Figure 8. Horizontal Waveforms
To improve the pull–in and noise characteristics of the first
PLL, the phase detector current is increased when the
vertical lock indicator signals an unlocked condition and is
decreased when locked. This increases the loop bandwidth
and pull–in range when out of lock, and decreases the loop
bandwidth when in lock, thus improving the noise
performance. In addition, the phase detector current during
the vertical period is reduced in order to minimize the
disturbance to the horizontal caused by the longer period
vertical phase detector pulses.
31.5kHz
Oscillator
12
13
15
17
14
SLICE
Divide
by 2
Divide
by 2
SLICE
Output
Vary
SLICE
Level
(Phase)
Phase
Detector 1
Deflection
Flyback
Phase
Detector 2
Vary
Frequency
Sync
Figure 7. Horizontal Oscillator Systems


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