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ADF4193BCPZ-RL7 датащи(PDF) 7 Page - Analog Devices

номер детали ADF4193BCPZ-RL7
подробное описание детали  Low Phase Noise, Fast Settling PLL Frequency Synthesizer
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ADF4193
Rev. B | Page 7 of 28
Pin No.
Mnemonic
Description
23
RSET
Connecting a resistor between this pin and GND sets the charge pump output current. The nominal voltage bias at
the RSET pin is 0.55 V. The relationship between ICP and RSET is
ICP = 0.25/RSET
So, with RSET = 2.4 kΩ, ICP = 104 μA.
24
VP2
Power Supply Pin for the Charge Pump. Nominally 5 V, should be at the same voltage at VP1. A 0.1 μF decoupling
capacitor to ground should be placed as close as possible to this pin.
25
AIN−
Differential Amplifier’s Negative Input Pin.
26
CPOUT−
Differential Charge Pump’s Negative Output Pin. Should be connected to AIN− and the loop filter.
27
SW2
Fast Lock Switch 2. This switch is closed to SWGND while the SW1/2 timeout counter is active.
28
SWGND
Common for SW1 and SW2 Switches. Should be connected to the ground plane.
29
SW1
Fast Lock Switch 1. This switch is closed to SWGND while the SW1/2 timeout counter is active.
30
CPOUT+
Differential Charge Pump’s Positive Output Pin. Should be connected to AIN+ and the loop filter.
31
AIN+
Differential Amplifier’s Positive Input Pin.
32
VP3
Power Supply Pin for the Differential Amplifier. This can range from 5.0 V to 5.5 V. A 0.1 μF decoupling capacitor to
ground should be placed as close as possible to this pin. Also requires a 10 μF decoupling capacitor to ground.


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