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ADF7020-1BCPZ-RL датащи(PDF) 11 Page - Analog Devices

номер детали ADF7020-1BCPZ-RL
подробное описание детали  High Performance FSK/ASK Transceiver IC
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ADF7020-1BCPZ-RL датащи(HTML) 11 Page - Analog Devices

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ADF7020-1
Rev. 0 | Page 11 of 48
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
VCOIN
CREG1
VDD1
RFOUT
RFGND
RFIN
RFINB
RLNA
VDD4
RSET
CREG4
GND4
DATA CLK
DATA I/O
INT/LOCK
VDD2
CREG2
ADCIN
GND2
SCLK
SREAD
SDATA
SLE
35
CLKOUT
36
34
33
32
31
30
29
28
27
26
25
ADF7020-1
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
Figure 6. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VCOIN
VCO Input Pin. The tuning voltage on this pin determines the output frequency of the voltage controlled
oscillator (VCO). The higher the tuning voltage, the higher the output frequency.
2
CREG1
Regulator Voltage for PA Block. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this pin
and ground for regulator stability and noise rejection.
3
VDD1
Voltage Supply for PA Block. Decoupling capacitors of 0.1 μF and 10 pF should be placed as close as possible to
this pin. All VDD pins should be tied together.
4
RFOUT
PA Output Pin. The modulated signal is available at this pin. Output power levels are from −20 dBm to +13 dBm.
The output should be impedance matched to the desired load using suitable components. See the Transmitter
section.
5
RFGND
Ground for Output Stage of Transmitter. All GND pins should be tied together.
6
RFIN
LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA input
to ensure maximum power transfer. See the LNA/PA Matching section.
7
RFINB
Complementary LNA Input. See the LNA/PA Matching section.
8
RLNA
External Bias Resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance.
9
VDD4
Voltage Supply for LNA/MIXER Block. This pin should be decoupled to ground with a 10 nF capacitor.
10
RSET
External Resistor to Set Charge Pump Current and Some Internal Bias Currents. Use 3.6 kΩ with 5% tolerance.
11
CREG4
Regulator Voltage for LNA/MIXER Block. A 100 nF capacitor should be placed between this pin and GND for
regulator stability and noise rejection.
12
GND4
Ground for LNA/MIXER Block.
13 to 18
MIX/FILT
Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left
unconnected.
19, 22
GND4
Ground for LNA/MIXER Block.
FILT/TEST_A
Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left
unconnected.
20, 21,
23
24
CE
Chip Enable. Bringing CE low puts the ADF7020-1 into complete power-down. Register values are lost when CE
is low, and the part must be reprogrammed once CE is brought high.
25
SLE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the
four latches. A latch is selected using the control bits.
26
SDATA
Serial Data Input. The serial data is loaded MSB first, with the 2 LSBs as the control bits. This pin is a high
impedance CMOS input.


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