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AD5645RBRUZ-REEL7 датащи(PDF) 9 Page - Analog Devices

номер детали AD5645RBRUZ-REEL7
подробное описание детали  Quad, 12-/14-/16-Bit nanoDACs with 5ppm/째C On-chip Ref, I2C Interface
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
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AD5645RBRUZ-REEL7 датащи(HTML) 9 Page - Analog Devices

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Preliminary Technical Data
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. PrA. | Page 9 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
LDAC
ADDR1
VDD
VOUTA
VOUTC
POR
VREFIN/VREFOUT
SCL
SDA
GND
VOUTB
VOUTD
CLR
ADDR2
1
2
3
4
5
6
7
14
13
12
11
10
9
8
AD5625(R)
AD5645R
AD5665(R)
TOP VIEW
(Not to Scale)
NOTE: VREFOUT ONLY ON -R VERSIONS
VOUTA
VOUTB
GND
VOUTC
VOUTD
VREFIN/VREFOUT
VDD
SDA
SCL
ADDR
1
2
3
4
5
10
9
8
7
6
AD5625(R)
AD5645R
AD5665(R)
TOP VIEW
(Not to Scale)
NOTE: VREFOUT ONLY ON -R VERSIONS
Pin Configuration (14-pin)
Pin Configuration (10-pin)
Figure 3. Pin Configurations
Table 7. Pin Function Descriptions
Pin No.
(14-pin)
Pin No.
(10-pin)
Mnemonic
Description
1
n/a
LDAC
Active low load DAC pin.
2
n/a
ADDR1
Three-state address input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address
(see Table 6).
3
9
VDD
Power supply input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be
decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
4
1
VOUTA
Analog output voltage from DAC C. The output amplifier has rail-to-rail operation.
5
4
VOUTC
Analog output voltage from DAC D. The output amplifier has rail-to-rail operation.
6
n/a
POR
Power-on reset.
7
10
VREFIN/VREFOUT
The AD5625R/AD5645R/AD5665R, AD5625/AD5665 have a common pin for reference input and
reference output. The internal reference and reference output are only available on suffix ---R
versions. When using the internal reference, this is the reference output pin. When using an external
reference, this is the reference input pin. The default for this pin is as a reference input.
8
n/a
ADDR2
Three-state address input. Sets bits A3 and A2 of the 7-bit slave address (see Table 6).
9
n/a
CLR
Asynchronous clear input. The
CLR input is falling edge sensitive. . While CLR is low, all LDAC
pulses are ignored. When
CLR is activated, zero scale is loaded to all input and DAC registers. This
clears the output to 0 V. The part exits clear code mode on the 24th falling edge of the next write to
the part. If
CLR is activated during a write sequence, the write is aborted.
10
5
VOUTD
Analog output voltage from DAC A. The output amplifier has rail-to-rail operation.
11
2
VOUTB
Analog output voltage from DAC B. The output amplifier has rail-to-rail operation.
12
3
GND
Ground reference point for all circuitry on the part.
13
8
SDA
Serial data line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit
input register. It is a bidirectional, open-drain data line that should be pulled to the supply with an
external pull-up resistor.
14
7
SCL
Serial clock line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit
input register.
n/a
6
ADDR
Three-state address input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address.


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