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AD7938BSU-6REEL7 датащи(PDF) 7 Page - Analog Devices |
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AD7938BSU-6REEL7 датащи(HTML) 7 Page - Analog Devices |
7 / 32 page AD7938-6 Rev. 0 | Page 7 of 32 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DB0 1 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 DB1 2 DB2 3 DB3 4 DB4 5 DB5 6 DB6 7 DB7 8 VIN1 24 VIN0 23 VREFIN/VREFOUT 22 AGND 21 20 19 WR 18 CONVST 17 AD7938-6 TOP VIEW (Not to Scale) RD CS PIN 1 IDENTIFIER Figure 2. Pin Configuration Table 4. Pin Function Description Pin No Mnemonic Function 1 to 8 DB0 to DB7 Data Bits 0 to 7. Three-state parallel digital I/O pins that provide the conversion result and also allow the control and shadow registers to be programmed. These pins are controlled by CS, RD, and WR. The logic high/low voltage levels for these pins are determined by the VDRIVE input. 9 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the parallel interface of the AD7938-6 operates. This pin should be decoupled to DGND. The voltage at this pin may be different to that at VDD but should never exceed VDD by more than 0.3 V. 10 DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7938-6. This pin should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 11 DB8/HBEN Data Bit 8/High Byte Enable. When W/B is high, this pin acts as Data Bit 8, a three-state I/O pin that is controlled by CS, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte of data being written to or read from the AD7938-6 is on DB0 to DB7. When HBEN is high, the top four bits of the data being written to or read from the AD7938-6 are on DB0 to DB3. When reading from the device, DB4 to DB6 of the high byte contains the ID of the channel to which the conversion result corresponds (see the channel address bits in Table 8). When writing to the device, DB4 to DB7 of the high byte must be all 0s. 12 to 14 DB9 to DB11 Data Bits 9 to 11. Three-state parallel digital I/O pins that provide the conversion result and also allow the control and shadow registers to be programmed in word mode. These pins are controlled by CS, RD, and WR. The logic high/low voltage levels for these pins are determined by the VDRIVE input. 15 BUSY Busy Output. Logic output indicating the status of the conversion. The BUSY output goes high following the falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is complete and the result is available in the output register, the BUSY output goes low. The track-and-hold returns to track mode just prior to the falling edge of BUSY on the 13th rising edge of SCLK, see Figure 35. 16 CLKIN Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the AD7938-6 takes 13 clock cycles + t2. The frequency of the master clock input therefore determines the conversion time and achievable throughput rate. The CLKIN signal may be a continuous or burst clock. 17 CONVST Conversion Start Input. A falling edge on CONVST is used to initiate a conversion. The track-and-hold goes from track to hold mode on the falling edge of CONVST and the conversion process is initiated at this point. Following power-down, when operating in autoshutdown or autostandby modes, a rising edge on CONVST is used to power-up the device. 18 WR Write Input. Active low logic input used in conjunction with CS to write data to the internal registers. 19 RD Read Input. Active low logic input used in conjunction with CS to access the conversion result. The conversion result is placed on the data bus following the falling edge of RD read while CS is low. 20 CS Chip Select. Active low logic input used in conjunction with RD and WR to read conversion data or to write data to the internal registers. |
Аналогичный номер детали - AD7938BSU-6REEL7 |
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Аналогичное описание - AD7938BSU-6REEL7 |
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