AD9927 datasheet(7/100 Pages) AD

номер детали	AD9927

подробное описание детали	14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator

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AD9927

Rev. 0 | Page 7 of 100

VERTICAL DRIVER SPECIFICATIONS

VH1, VH2 = 15 V. VM1, VM2, VMM = 0 V. VL1, VL2, VLL = −7.5 V. CL shown in load model, 25°C.

Table 5.

Parameter

Symbol

Min

Typ

Max

Unit

V-DRIVER OUTPUTS (SIMPLIFIED LOAD CONDITIONS, 3000 pF to GROUND)

Delay Time, VL to VM and VM to VH

tPLM, tPMH

35

ns

Delay Time, VM to VL and VH to VM

tPML, tPHM

35

ns

Rise Time, VL to VM

tRLM

125

ns

Rise Time, VM to VH

tRMH

260

ns

Fall Time, VM to VL

tFML

220

ns

Fall Time, VH to VM

tFHM

125

ns

Output Currents

@ −7.25 V

10

mA

@ −0.25 V

−22

mA

@ +0.25 V

22

mA

@ +14.75 V

−10

mA

RON

35

Ω

SUBCK OUTPUT (SIMPLIFIED LOAD CONDITIONS, 1000 pF to GROUND)

Delay Time, VLL to VH

tPLH

25

ns

Delay Time, VH to VLL

tPHL

30

ns

Delay Time, VLL to VMM

tPLM

25

ns

Delay Time, VMM to VH

tPMH

25

ns

Delay Time, VH to VMM

tPHM

30

ns

Delay Time, VMM to VLL

tPML

25

ns

Rise Time, VLL to VH

tRLH

40

ns

Rise Time, VLL to VMM

tRLM

45

ns

Rise Time, VMM to VH

tRMH

30

ns

Fall Time, VH to VLL

tFHL

40

ns

Fall Time, VH to VMM

tFHM

90

ns

Fall Time, VMM to VLL

tFML

25

ns

Output Currents

@ −7.25 V

20

mA

@ −0.25 V

−12

mA

@ +0.25 V

12

mA

@ +14.75 V

−20

mA

RON

35

Ω

V-DRIVER

INPUT

tRLM, tRMH, tRLH

50%

10%

90%

tPLM, tPMH, tPLH

V-DRIVER

OUTPUT

10%

50%

90%

tFML, tFHM, tFHL

tPML, tPHM, tPHL

Figure 2. Definition of V-Driver Timing Specifications

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производитель	номер детали	датащи	подробное описание детали
Analog Devices	AD9927	843Kb / 100P	14-Bit CCD Signal Processor with V-Driver and Precision Timing Generator REV. 0

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