Triscend A7S Configurable System-on-Chip Platform
SUBJECT TO CHANGE
8
TCH305-0001-002
Table 3. A7S Development Boards.
Supplier
Part Number
Triscend Corporation
THW-KIT-720
Embedded Performance Inc. (EPI)
Dev-A7
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Figure 3 presents a detailed view of the entire Triscend A7S development flow. FastChip
is a Windows-based application and operates on most PC-compatible computers with the
recommended minimum 192Mbytes of RAM memory. The Triscend FastChip develop-
ment system provides design integration and configuration capabilities, working in con-
junction with third-party logic design and software development tools.
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FastChip includes a powerful Soft Module library of commonly used embedded systems
functions like additional UARTs, timers, various bus interfaces, etc. Likewise, FastChip
includes libraries that allow designers to create custom functions using third-part logic de-
sign and simulation tools. Designs imported into FastChip via an EDIF 2.0.0 netlist be-
come FastChip modules.
FastChip also exports a CSoC designs for either VHDL or Verilog logic simulation pur-
poses. A Triscend-provided bus functional model simulates traffic on the A7S’s internal
CSI bus.
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After defining the A7S’s logic, FastChip’s Bind utility creates the physical hardware im-
plementation for the CSoC device. Similarly, FastChip’s Generate utility allocates ad-
dresses for any functions attached to the Configurable System Interconnect (CSI) bus and
creates an application programming model for a third-party ARM compiler. This model in-
cludes register definitions for both standard ARM7TDMI functions and any custom hard-
ware.
FastChip combines the output from the Bind utility and the object code from the
ARM7TDMI compiler to create a CSoC initialization image. Using this image, FastChip ei-
ther directly downloads to an A7S device or programs external Flash memory attached to
the A7. Optionally, the initialization image can be saved as an Intel Hex file four use with
an external device programmer.
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Furthermore, FastChip provides a real-time, in-system debugging environment using the
actual A7S production silicon with the actual system hardware and application software.
FastChip drives a supported JTAG-based debugger/emulator and provides interfaces to
third-party source-level debuggers. Via a source-level debugger, software developers
have register-level access to the A7S device, complete with breakpoints and trace. Fast-
Chip’s Debug utility also provides logic debugging capabilities, including the ability to
probe flip-flop values and the outputs of CSL cells.
FastChip’s Configure and Download/Debug utilities are packaged as a separate, stand-
alone application called FastChip Device Link (FDL), providing software developers with
necessary software development capabilities without the complexity of the entire FastChip
CSoC development system.