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CS42L52 датащи(PDF) 7 Page - Cirrus Logic |
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CS42L52 датащи(HTML) 7 Page - Cirrus Logic |
7 / 82 page DS680A1 7 CS42L52 6.40.4 Speaker Attenuation ............................................................................................................ 74 6.41 Charge Pump Frequency (Address 34h) ...................................................................................... 74 6.41.1 Charge Pump Frequency .................................................................................................... 74 7. ANALOG PERFORMANCE PLOTS ....................................................................................................75 7.1 Headphone THD+N versus Output Power Plots ............................................................................ 75 8. EXAMPLE SYSTEM CLOCK FREQUENCIES .................................................................................... 77 8.1 Auto Detect Enabled .................................................................................................................... 77 8.2 Auto Detect Disabled .................................................................................................................... 77 9. PCB LAYOUT CONSIDERATIONS ..................................................................................................... 78 9.1 Power Supply, Grounding ............................................................................................................... 78 9.2 QFN Thermal Pad .......................................................................................................................... 78 10. ADC & DAC DIGITAL FILTERS ........................................................................................................ 79 11. PARAMETER DEFINITIONS .............................................................................................................. 80 12. PACKAGE DIMENSIONS .................................................................................................................. 81 THERMAL CHARACTERISTICS ........................................................................................................81 13. ORDERING INFORMATION .............................................................................................................. 82 14. REFERENCES .................................................................................................................................... 82 15. REVISION HISTORY .......................................................................................................................... 82 LIST OF FIGURES Figure 1. Typical Connection Diagram ...................................................................................................... 10 Figure 2. Headphone Output Test Load .................................................................................................... 19 Figure 3. Serial Audio Interface Timing ..................................................................................................... 21 Figure 4. Control Port Timing - I²C ............................................................................................................ 22 Figure 5. Analog Input Signal Flow ........................................................................................................... 26 Figure 6. Single-Ended MIC Configuration ............................................................................................... 27 Figure 7. Differential MIC Configuration .................................................................................................... 27 Figure 8. ALC ............................................................................................................................................ 28 Figure 9. Noise Gate Attenuation .............................................................................................................. 28 Figure 10. DSP Engine Signal Flow .......................................................................................................... 29 Figure 11. PWM Output Stage .................................................................................................................. 30 Figure 12. Analog Output Stage ................................................................................................................ 30 Figure 13. Beep Configuration Options ..................................................................................................... 31 Figure 14. Peak Detect & Limiter .............................................................................................................. 32 Figure 15. Battery Compensation ............................................................................................................. 34 Figure 16. I²S Format ................................................................................................................................ 36 Figure 17. Left-Justified Format ................................................................................................................ 36 Figure 18. Right-Justified Format (DAC only) ........................................................................................... 36 Figure 19. DSP Mode Format) .................................................................................................................. 36 Figure 20. Control Port Timing, I²C Write .................................................................................................. 38 Figure 21. Control Port Timing, I²C Read .................................................................................................. 38 Figure 22. THD+N vs. Output Power per Channel at 1.8 V (16 Ω load) ................................................... 75 Figure 23. THD+N vs. Output Power per Channel at 2.5 V (16 Ω load) ................................................... 75 Figure 24. THD+N vs. Output Power per Channel at 1.8 V (32 Ω load) ................................................... 76 Figure 25. THD+N vs. Output Power per Channel at 2.5 V (32 Ω load) ................................................... 76 Figure 26. ADC Passband Ripple ............................................................................................................. 79 Figure 27. ADC Stopband Rejection ......................................................................................................... 79 Figure 28. ADC Transition Band ............................................................................................................... 79 Figure 29. ADC Transition Band Detail ..................................................................................................... 79 Figure 30. DAC Passband Ripple ............................................................................................................. 79 Figure 31. DAC Stopband ......................................................................................................................... 79 Figure 32. DAC Transition Band ............................................................................................................... 79 Figure 33. DAC Transition Band (Detail) ................................................................................................... 79 |
Аналогичный номер детали - CS42L52 |
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Аналогичное описание - CS42L52 |
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