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SN74GTLPH16927GR датащи(PDF) 3 Page - Texas Instruments |
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SN74GTLPH16927GR датащи(HTML) 3 Page - Texas Instruments |
3 / 19 page SN74GTLPH16927 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS SCES413 – OCTOBER 2002 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 terminal assignments 12 34 5 6 A A1 OE DIR FSTA BIAS VCC B1 B A3 A2 GND GND B2 B3 C A5 A4 VCC VREF B4 B5 D A7 A6 GND GND B6 B7 E A9 A8 B8 B9 F A10 A11 B11 B10 G A12 A13 GND GND B13 B12 H A14 A15 VCC CMS B15 B14 J A16 A17 GND GND B17 B16 K A18 CLKOUT CKOE SYSCLK SSCLK B18 functional description The SN74GTLPH16927 is a medium-drive (50 mA), 18-bit bus transceiver containing D-type latches and D-type flip-flops for data-path operation in transparent or latched modes and can replace any of the functions shown in Table 1. Data polarity is noninverting. Table 1. SN74GTLPH16927 Bus-Transceiver Replacement Functions FUNCTION 8 BIT 9 BIT 10 BIT 16 BIT 18 BIT Transceiver ’245, ’623, ’645 ’863 ’861 ’16245, ’16623 ’16863 Buffer/driver ’241, ’244, ’541 ’827 ’16241, ’16244, ’16541 ’16825 Latched transceiver ’543 ’16543 ’16472 Latch ’373, ’573 ’843 ’841 ’16373 ’16843 SN74GTLPH16927 bus transceiver replaces all above functions Additionally, the device allows for conversion of the system clock (SYSCLK) to GTLP signal levels (SSCLK) and LVTTL signal levels (CLKOUT). It also provides conversion of a GTLP source-synchronous clock to LVTTL signal levels (CLKOUT). The device allows for conversion of the LVTTL system clock (SYSCLK) to GTLP (SSCLK) and LVTTL (CLKOUT) signal levels when used as the transmitter and GTLP source-synchronous clock (SSCLK) to LVTTL (CLKOUT) signal levels when used as the receiver in source-synchronous applications. Source-synchronous operation removes time-of-flight restrictions and allows for increased data throughput. CMS is used to switch between system-synchronous mode and clock-synchronous mode. The clock output-enable (CKOE) input is used to switch between latched and transparent mode. Data flow in each direction is controlled by CKOE, clock (SYSCLK or SSCLK), DIR, and OE. OE controls the 18 bits of data. The CLKOUT/SSCLK buffered clock path for the A-to-B and B-to-A directions is controlled by CKOE. In the data-isolation mode (OE high, CKOE low), A data can be stored in one register and/or B data can be stored in the other register. GQL PACKAGE (TOP VIEW) J H G F E D C B A 2 13 4 6 5 K |
Аналогичный номер детали - SN74GTLPH16927GR |
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Аналогичное описание - SN74GTLPH16927GR |
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