www.fairchildsemi.com

2

Unit Loading/Fan Out

Functional Description

The 74F164A is an edge-triggered 8-bit shift register with

serial data entry and an output from each of the eight

stages. Data is entered serially through one of two inputs

(A or B); either of these inputs can be used as an active

HIGH Enable for data entry through the other input. An

unused input must be tied HIGH.

Each LOW-to-HIGH transition on the Clock (CP) input

ical AND of the two data inputs (A • B) that existed before

the rising clock edge. A LOW level on the Master Reset

(MR) input overrides all other inputs and clears the register

asynchronously, forcing all Q outputs LOW.

Mode Select Table

H(h)

= HIGH Voltage Levels

L(l)

= LOW Voltage Levels

X

= Immaterial

one setup time prior to the LOW-to-HIGH clock transition.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Pin Names

Description

U.L.

HIGH/LOW

A, B

Data Inputs

1.0/1.0

20

µA/−0.6 mA

CP

Clock Pulse Input (Active Rising Edge)

1.0/1.0

20

µA/−0.6 mA

MR

Master Reset Input (Active LOW)

1.0/1.0

20

µA/−0.6 mA

Outputs

50/33.3

−1 mA/20 mA

Operating

Inputs

Outputs

Mode

MR

AB

Reset (Clear)

L

X

X

L

L-L

Hl

l

L

Shift

H

l

h

L

Hh

l

L

Hh

h

H