MC10EP29DTG datasheet(1/11 Pages) ONSEMI

номер детали	MC10EP29DTG

подробное описание детали	3.3V / 5V ECL Dual Differential Data and Clock D Flip?묯lop With Set and Reset

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December, 2006 − Rev. 4

1

Publication Order Number:

MC10EP29/D

MC10EP29, MC100EP29

3.3V / 5VECL Dual

Differential Data and Clock

D Flip−Flop With Set and

Reset

Description

The MC10/100EP29 is a dual master−slave flip−flop. The device

features fully differential Data and Clock inputs as well as outputs.

The MC10/100EP29 is functionally equivalent to the

MC10/100EL29. Data enters the master latch when the clock is LOW

and transfers to the slave upon a positive transition on the clock input.

The differential inputs have special circuitry which ensures device

stability under open input conditions. When both differential inputs

are left open the D input will pull down to VEE and the D input will

bias around VCC/2. The outputs will go to a defined state, however the

state will be random based on how the flip flop powers up.

Both flip flops feature asynchronous, overriding Set and Reset

inputs. Note that the Set and Reset inputs cannot both be HIGH

simultaneously.

The VBB pin, an internally generated voltage supply, is available to

this device only. For single-ended input conditions, the unused

differential input is connected to VBB as a switching reference voltage.

VBB may also rebias AC coupled inputs. When used, decouple VBB

and VCC via a 0.01 mF capacitor and limit current sourcing or sinking

to 0.5 mA. When not used, VBB should be left open.

The 100 Series contains temperature compensation.

Features

• Maximum Frequency > 3 GHz Typical

• 500 ps Typical Propagation Delays

• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V

with VEE = 0 V

• NECL Mode Operating Range: VCC = 0 V

with VEE = −3.0 V to −5.5 V

• Open Input Default State

• Safety Clamp on Inputs

• These are Pb−Free Devices

MARKING

DIAGRAM*

TSSOP−20

DT SUFFIX

CASE 948E

xxx

= MC10 or 100

A

= Assembly Location

L

= Wafer Lot

Y

= Year

W

= Work Week

G

= Pb−Free Package

*For additional marking information, refer to

Application Note AND8002/D.

http://onsemi.com

(Note: Microdot may be in either location)

See detailed ordering and shipping information in the package

dimensions section on page 8 of this data sheet.

ORDERING INFORMATION

XXXX

EP29

ALYWG

G

1

20

QFN−20

MN SUFFIX

CASE 485E

XXXX

EP29

ALYWG

G

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ON Semiconductor	MC10EP29DTG	111Kb / 10P	ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset April, 2014 ??Rev. 9

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