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2

Connection Diagram

(Top Thru View)

Pin Descriptions

FBGA Pin Assignments

Truth Table

H

= Logic HIGH

X

= Don’t Care, but not floating

Z

= High Impedance

L

= Logic LOW

↑ = LOW-to-HIGH Clock Transition

Note 3: Output level before the indicated steady-state input conditions

were established provided that CLK was HIGH before LE went LOW.

Note 4: Output level before the indicated steady-state input conditions

were established.

Logic Diagram

Pin Names

Description

Output Enable Input (Active LOW)

Latch Enable Input

Clock Input

Data Inputs

Data Inputs

3-STATE Outputs

3-STATE Outputs

1

234

56

A

NC

NC

B

NC

GND

C

GND

GND

D

E

GND

GND

F

GND

GND

G

H

GND

GND

J

K

NC

NC

GND

NC

NC

L

NC

GND

M

GND

GND

N

P

GND

GND

R

GND

GND

T

U

GND

GND

V

W

GND

Inputs

Outputs

H

XXX

Z

LH

X

L

L

LH

X

H

H

LL

↑

LL

LL

↑

HH

LL

H

X

LLL

X