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SN74V215 датащи(PDF) 5 Page - Texas Instruments

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номер детали SN74V215
подробное описание детали  512 X 18, 1024 X 18, 2048 X 18, 4096 X 18 DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
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SN74V215 датащи(HTML) 5 Page - Texas Instruments

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SN74V215, SN74V225, SN74V235, SN74V245
512
× 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC
 FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
WEN
20
I
Write enable. When WEN is low, data is written into the FIFO on every low-to-high transition of WCLK.
When WEN is high, the FIFO holds the previous data. Data is not written into the FIFO if FF is low.
WXI
21
I
Width expansion. In the single-device or width-expansion configuration, WXI, together with FL and RXI,
determines if the mode is standard mode or FWFT mode, as well as whether the PAE/PAF flags are
synchronous or asynchronous (see Table 4). In the daisy-chain depth-expansion configuration, WXI is
connected to WXO (write expansion out) of the previous device.
WXO/HF
26
O
Half-full flag. In the single-device or width-expansion configuration, the device is more than half full when
HF is low. In the depth-expansion configuration, a pulse is sent from WXO to WXI of the next device when
the last location in the FIFO is written.
detailed description
INPUTS:
DATA IN (D0–D17)
Data inputs for 18-bit-wide data.
CONTROLS:
RESET (RS)
Reset is accomplished when RS is taken low. During reset, both internal read and write pointers are set to the
first location. A reset is required after power up before a write operation can take place. The half-full flag (HF)
and programmable almost-full flag (PAF) is reset to high after tRSF. The programmable almost-empty flag (PAE)
is reset to low after tRSF. The full flag (FF) resets to high. The empty flag (EF) resets to low in standard mode,
but resets to high in FWFT mode. During reset, the output register is initialized to all zeros, and the offset
registers are initialized to their default values.
WRITE CLOCK (WCLK)
A write cycle is initiated on the low-to-high transition of WCLK. Data setup and hold times must be met with
respect to the low-to-high transition of WCLK.
The write and read clocks can be asynchronous or coincident.
WRITE ENABLE (WEN)
When WEN is low, data can be loaded into the FIFO RAM array on the rising edge of every WCLK cycle if the
device is not full. Data is stored in the RAM array sequentially and independently of any ongoing read operation.
When WEN is high, no new data is written in the RAM array on each WCLK cycle.
To prevent data overflow in the standard mode, FF goes low, inhibiting further write operations. Upon completion
of a valid read cycle, FF goes high, allowing a write to occur. The FF flag is updated on the rising edge of WCLK.
To prevent data overflow in the FWFT mode, IR goes high, inhibiting further write operations. Upon completion
of a valid read cycle, IR goes low, allowing a write to occur. The IR flag is updated on the rising edge of WCLK.
WEN is ignored when the FIFO is full in either FWFT or standard mode.
READ CLOCK (RCLK)
Data can be read on the outputs on the low-to-high transition of RCLK when OE is low.
The write and read clocks can be asynchronous or coincident.


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