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CA3224E датащи(PDF) 3 Page - Intersil Corporation

номер детали CA3224E
подробное описание детали  Automatic Picture Tube Bias Control Circuit
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производитель  INTERSIL [Intersil Corporation]
домашняя страница  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CA3224E датащи(HTML) 3 Page - Intersil Corporation

  CA3224E_02 Datasheet HTML 1Page - Intersil Corporation CA3224E_02 Datasheet HTML 2Page - Intersil Corporation CA3224E_02 Datasheet HTML 3Page - Intersil Corporation CA3224E_02 Datasheet HTML 4Page - Intersil Corporation CA3224E_02 Datasheet HTML 5Page - Intersil Corporation CA3224E_02 Datasheet HTML 6Page - Intersil Corporation  
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3
Test Circuit
Device Description and Operation (See Figures
1, 2, 4 and 5)
During the vertical retrace interval, 13 horizontal sync pulses
are counted. On the 14th sync pulse the auto-bias pulse
output goes high. This is used to set the RGB drive of the
companion chroma/luma circuit to black level. The auto-bias
pulse stays high for 7 horizontal periods during the auto-bias
cycle.
On the 15th horizontal sync pulse, the internal logic initiates the
setup interval. During the setup interval, the cathode current is
increased to a reference value (A in Figure 5) through the
action of the grid pulse. The cathode current causes a voltage
drop across RS. This voltage drop, together with the program
pulse output results in a reference voltage at VS (summing
point) which causes capacitor C1 to charge to a voltage
proportional to the reference cathode current. The setup
interval lasts for 3 horizontal periods.
On the 18th horizontal sync pulse the grid pulse output
goes high, which through the grid pulse amplifier/inverter,
causes the cathode current to decrease. The decrease in
cathode current results in a positive recovered voltage
pulse with respect to the setup reference level at the VS
summing point. The positive recovered voltage pulse is
summed with a negative voltage pulse caused by the
program pulse output going low (cutting off Diode D1 and
switching in resistors R1 and R2). Any difference between
the positive and negative pulses is fed through capacitor
C1 to the transconductance amplifier. The difference signal
is amplified in the transconductance amplifier and charges
the hold capacitor C2, which, through the buffer amplifier,
adjusts the bias on the driver circuit.
Components RS, R1, and R2 must be chosen such that the
program pulse and the recovered pulse just cancel at the
desired cathode cutoff level.
VOUT2
3.65K
0.12
µF
A
S1
B
122
21
20
19
18
17
16
15
14
13
12
3.65K
0.12
µF
A
S1
B
VOUT1
3.65K
0.12
µF
A
S1
B
VOUT3
47
µF
3.32K
+20V
1.50K
+10V
1.5K
A
S2
B
2
3
4
5
6
7
8
9
10
11
VIN1
VIN2
VIN3
VERTICAL
INPUT
HORIZONTAL
INPUT
CA3224E
0.047
µF
0.047
µF
0.047
µF
20K
1.0K
+
+10V
VBIAS
CHAN
1 IN
FREQ
COMP
HOLD
CAPACITOR
CHAN
1 OUT
CHAN
2 IN
FREQ
COMP
HOLD
CAPACITOR
CHAN
2 OUT
CHAN
3 IN
FREQ
COMP
HOLD
CAPACITOR
CHAN
3 OUT
2
3
21
20
4
5
19
18
6
7
17
16
x 1
x 1
x 1
+
-
gM
BUFFER
AMP
AMPLIFER
NO. 3
BUFFER
AMP
AMPLIFER
NO. 2
BUFFER
AMP
AMPLIFER
NO. 1
1
1
22
3
3
3
2
1
VREF
MODE
SWITCH
LOGIC
BIAS
1
9
22
15
8
10
11
12
13
14
GND
GND
VCC
VREF
BYPASS
VERT
IN
HORIZ
IN
AUTO
BIAS
LEVEL
ADJUST
AUTO
BIAS
PULSE
OUT
PROG
PULSE
OUT
GRID
PULSE
OUT
MODE SWITCH
STATE
SET-UP
SENSE
OPEN
1
2
3
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
+
-
gM
+
-
gM
CA3224E


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