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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AM29F016D-120DPC1 датащи(PDF) 3 Page - Advanced Micro Devices |
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AM29F016D-120DPC1 датащи(HTML) 3 Page - Advanced Micro Devices |
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3 / 12 page  2 Am29F016D Known Good Die June 11, 2002 SU P P L E MEN T GENERAL DESCRIPTION The Am29F016D in Known Good Die (KGD) form is a 16 Mbit, 5.0 volt-only Flash memory. AMD defines KGD as standard product in die form, tested for functionality and speed. AMD KGD products have the same reliability and quality as AMD products in packaged form. Am29F016D Features The Am29F016D is a 16 Mbit, 5.0 volt-only Flash memory organized as 2,097,152 bytes of 8 bits each. The 2 Mbytes of data are divided into 32 sectors of 64 Kbytes each for flexible erase capability. The 8 bits of data appear on DQ0–DQ7. The Am29F016D is manufactured using AMD’s 0.32 µm process tech- nology. This device is designed to be programmed in-system with the standard system 5.0 volt VCC supply. A 12.0 volt VPP is not required for program or erase operations. The device can also be programmed in standard EPROM programmers. The standard device offers an access time of 120 ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention, the device has separate chip enable (CE#), write enable (WE#), and output enable (OE#) controls. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Com- mands are written to the command register using stan- dard microprocessor write timings. Register contents serve as input to an internal state machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the pro- gramming and erase operations. Reading data out of the device is similar to reading from 12.0 volt Flash or EPROM devices. The device is programmed by executing the program command sequence. This invokes the Embedded Program algorithm—an internal algorithm that automat- ically times the program pulse widths and verifies proper cell margin. The device is erased by executing the erase command sequence. This invokes the Embedded Erase algorithm—an internal algorithm that automatically pre- programs the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. A sector is typically erased and verified within one second. The device is erased when shipped from the factory. The hardware sector group protection feature disables both program and erase operations in any combination of the eight sector groups of memory. A sector group consists of four adjacent sectors. The Erase Suspend feature enables the system to put erase on hold for any period of time to read data from, or program data to, a sector that is not being erased. True background erase can thus be achieved. The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations during power transitions. The host system can detect whether a program or erase cycle is complete by using the RY/BY# pin, the DQ7 (Data# Polling) or DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device automatically returns to the read mode. A hardware RESET# pin terminates any operation in progress. The internal state machine is reset to the read mode. The RESET# pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during either an Embedded Program or Embedded Erase algo- rithm, the device is automatically reset to the read mode. This enables the system’s microprocessor to read the boot-up firmware from the Flash memory. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highes t lev els of qualit y, r eliabilit y, and c o s t effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tun- neling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot elec- tron injection. Electrical Specifications Refer to the Am29F016D data sheet, publication number 21444, for full electrical specifications on the Am29F016D in KGD form. PRODUCT SELECTOR GUIDE Family Part Number Am29F016D KGD Speed Option (VCC = 5.0 V ± 10%) -120 Max Access Time, tACC (ns) 120 Max CE# Access, tCE (ns) 120 Max OE# Access, tOE (ns) 50 |
Аналогичный номер детали - AM29F016D-120DPC1 |
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Аналогичное описание - AM29F016D-120DPC1 |
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