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AM29BDD160GB28CPBK датащит (Datasheet) 4 Page - Advanced Micro Devices

№ деталь AM29BDD160GB28CPBK
подробность  16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
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производитель  AMD [Advanced Micro Devices]
домашняя страница  http://www.amd.com
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Am29BDD160G
June 7, 2006
GENERAL DESCRIPTION
The Am29BDD160 is a 16 Megabit, 2.5 Volt-only sin-
gle power supply burst mode flash memory device.
The device can be configured for either 1,048,576
words in 16-bit mode or 524,288 double words in
32-bit mode. The device can also be programmed in
standard EPROM programmers. The device offers a
configurable burst interface to 16/32-bit microproces-
sors and microcontrollers.
To eliminate bus contention, each device has separate
chip enable (CE#), write enable (WE#) and output en-
able (OE#) controls. Additional control inputs are re-
quired for synchronous burst operations: Load Burst
Address Valid (ADV#), and Clock (CLK).
Each device requires only a single 2.5 or 2.6 Volt
power supply (2.5 V to 2.75 V) for both read and write
functions. A 12.0-volt V
PP is not required for program
or erase operations, although an acceleration pin is
available if faster programming performance is re-
quired.
The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard.
The software command set is compatible with the
command sets of the 5 V Am29F and 3 V Am29LV
Flash families. Commands are written to the command
register using standard microprocessor write timing.
Register contents serve as inputs to an internal
state-machine that controls the erase and program-
ming circuitry. Write cycles also internally latch ad-
dresses and data needed for the programming and
erase operations. Reading data out of the device is
similar to reading from other Flash or EPROM de-
vices.
The Unlock Bypass mode facilitates faster program-
ming times by requiring only two write cycles to pro-
gram data instead of four.
The Simultaneous Read/Write architecture provides
simultaneous operation by dividing the memory space
into two banks. The device can begin programming or
erasing in one bank, and then simultaneously read
from the other bank, with zero latency. This releases
the system from waiting for the completion of program
or erase operations. See Simultaneous Read/Write
Operations Overview and Restrictions on page 13.
The device provides a 256-byte SecSi™ (Secured
Silicon) Sector with an one-time-programmable
(OTP) mechanism.
In addition, the device features several levels of sector
protection, which can disable both the program and
erase operations in certain sectors or sector groups:
Persistent Sector Protection is a command sector
protection method that replaces the old 12 V con-
trolled protection method; Password Sector Protec-
tion is a highly sophisticated protection method that
requires a password before changes to certain sectors
or sector groups are permitted; WP# Hardware Pro-
tection prevents program or erase in the two outer-
most 8 Kbytes sectors of the larger bank.
The device defaults to the Persistent Sector Protection
mode. The customer must then choose if the Standard
or Password Protection method is most desirable. The
WP# Hardware Protection feature is always available,
independent of the other protection method chosen.
The VersatileI/O™ (V
CCQ) feature allows the output
voltage generated on the device to be determined
based on the V
IO level. This feature allows this device
to operate in the 1.8 V I/O environment, driving and re-
ceiving signals to and from other 1.8 V devices on the
same bus. In addition, inputs and I/Os that are driven
externally are capable of handling 3.6 V.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, by reading the DQ7 (Data# Polling), or DQ6 (tog-
gle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The password and
software sector protection feature disables both
program and erase operations in any combination of
sectors of memory. This can be achieved in-system at
VCC level.
The Program/Erase Suspend/Erase Resume fea-
ture enables the user to put erase on hold for any pe-
riod of time to read data from, or program data to, any
sector that is not selected for erasure. True back-
ground erase can thus be achieved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the
standby mode. Power consumption is greatly re-
duced in both these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunnelling.
The data is programmed using hot electron injection.




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