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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AM50DL128CH85IS датащи(PDF) 5 Page - SPANSION |
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AM50DL128CH85IS датащи(HTML) 5 Page - SPANSION |
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5 / 66 page  February 6, 2004 Am50DL128CH 3 ADV ANCE I N FO RMAT I O N TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5 Flash Memory Block Diagram . . . . . . . . . . . . . . . . 6 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7 Special Package Handling Instructions .................................... 7 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9 MCP Device Bus Operations . . . . . . . . . . . . . . . . 10 Table 1. Device Bus Operations—Flash Word Mode .....................11 Flash Device Bus Operations . . . . . . . . . . . . . . . 12 Word Configuration ................................................................. 12 Requirements for Reading Array Data ................................... 12 Writing Commands/Command Sequences ............................ 12 Accelerated Program Operation .......................................... 12 Autoselect Functions ........................................................... 12 Simultaneous Read/Write Operations with Zero Latency ....... 12 Standby Mode ........................................................................ 12 Automatic Sleep Mode ........................................................... 13 RESET#: Hardware Reset Pin ............................................... 13 Output Disable Mode .............................................................. 13 Table 2. Am29DL640H Sector Architecture ....................................14 Table 3. Bank Address ....................................................................17 Table 4. SecSi ™ Sector Addresses ...............................................17 Sector/Sector Block Protection and Unprotection .................. 18 Table 5. Am29DL640H Boot Sector/Sector Block Addresses for Pro- tection/Unprotection ........................................................................18 Write Protect (WP#) ................................................................ 18 Table 6. WP#/ACC Modes ..............................................................19 Temporary Sector Unprotect .................................................. 19 Figure 1. Temporary Sector Unprotect Operation ...........................19 Figure 2. In-System Sector Protect/Unprotect Algorithms ..............20 SecSi™ (Secured Silicon) Sector Flash Memory Region ............................................................ 21 Figure 3. SecSi Sector Protect Verify ..............................................22 Hardware Data Protection ...................................................... 22 Low V CC Write Inhibit ........................................................... 22 Write Pulse “Glitch” Protection ............................................ 22 Logical Inhibit ...................................................................... 22 Power-Up Write Inhibit ......................................................... 22 Common Flash Memory Interface (CFI) . . . . . . . 22 Table 7. CFI Query Identification String ..........................................23 Table 8. System Interface String .....................................................23 Table 9. Device Geometry Definition ..............................................24 Table 10. Primary Vendor-Specific Extended Query ......................25 Flash Command Definitions . . . . . . . . . . . . . . . . 26 Reading Array Data ................................................................ 26 Reset Command ..................................................................... 26 Autoselect Command Sequence ............................................ 26 Enter SecSi™ Sector/Exit SecSi Sector Command Sequence .............................................................. 26 Word Program Command Sequence ..................................... 27 Unlock Bypass Command Sequence .................................. 27 Figure 4. Program Operation ..........................................................28 Chip Erase Command Sequence ........................................... 28 Sector Erase Command Sequence ........................................ 28 Figure 5. Erase Operation ...............................................................29 Erase Suspend/Erase Resume Commands ........................... 29 Table 11. Am29DL640H Command Definitions ..............................30 Flash Write Operation Status . . . . . . . . . . . . . . . 31 DQ7: Data# Polling ................................................................. 31 Figure 6. Data# Polling Algorithm .................................................. 31 RY/BY#: Ready/Busy# ............................................................ 32 DQ6: Toggle Bit I .................................................................... 32 Figure 7. Toggle Bit Algorithm ........................................................ 32 DQ2: Toggle Bit II ................................................................... 33 Reading Toggle Bits DQ6/DQ2 ............................................... 33 DQ5: Exceeded Timing Limits ................................................ 33 DQ3: Sector Erase Timer ....................................................... 33 Table 12. Write Operation Status ................................................... 34 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 35 Figure 8. Maximum Negative Overshoot Waveform ...................... 35 Figure 9. Maximum Positive Overshoot Waveform ........................ 35 ESD Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 ESD Immunity ......................................................................... 36 Flash DC Characteristics . . . . . . . . . . . . . . . . . . 37 CMOS Compatible .................................................................. 37 pSRAM DC & Operating Characteristics . . . . . . 38 Flash DC Characteristics . . . . . . . . . . . . . . . . . . 39 Figure 10. I CC1 Current vs. Time (Showing Active and Automatic Sleep Currents) ............................................................. 39 Figure 11. Typical I CC1 vs. Frequency ............................................ 39 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 12. Test Setup .................................................................... 40 Figure 13. Input Waveforms and Measurement Levels ................. 40 pSRAM AC Characteristics . . . . . . . . . . . . . . . . . 41 CE#s Timing ........................................................................... 41 Figure 14. Timing Diagram for Alternating Between Pseudo SRAM to Flash ................................................... 41 Read-Only Operations ........................................................... 42 Figure 15. Read Operation Timings ............................................... 42 Hardware Reset (RESET#) .................................................... 43 Figure 16. Reset Timings ............................................................... 43 Erase and Program Operations .............................................. 44 Figure 17. Program Operation Timings .......................................... 45 Figure 18. Accelerated Program Timing Diagram .......................... 45 Figure 19. Chip/Sector Erase Operation Timings .......................... 46 Figure 20. Back-to-back Read/Write Cycle Timings ...................... 47 Figure 21. Data# Polling Timings (During Embedded Algorithms) . 47 Figure 22. Toggle Bit Timings (During Embedded Algorithms) ...... 48 Figure 23. DQ2 vs. DQ6 ................................................................. 48 Temporary Sector Unprotect .................................................. 49 Figure 24. Temporary Sector Unprotect Timing Diagram .............. 49 Figure 25. Sector/Sector Block Protect and Unprotect Timing Diagram ............................................................. 50 Alternate CE#f Controlled Erase and Program Operations .... 51 Figure 26. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings .......................................................................... 52 Read Cycle ............................................................................. 53 Figure 27. Pseudo SRAM Read Cycle ........................................... 53 Figure 28. Page Read Timing ........................................................ 54 Write Cycle ............................................................................. 55 Figure 29. Pseudo SRAM Write Cycle—WE# Control ................... 55 Figure 30. Pseudo SRAM Write Cycle—CE#1ps Control .............. 56 Figure 31. Pseudo SRAM Write Cycle— UB#s and LB#s Control .................................................................. 57 |
Аналогичный номер детали - AM50DL128CH85IS |
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Аналогичное описание - AM50DL128CH85IS |
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