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AM49DL6408H85IS датащи(PDF) 5 Page - SPANSION

номер детали AM49DL6408H85IS
подробное описание детали  64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (512 K x 16-Bit)
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March 12, 2004
Am49DL6408H
3
ADV ANCE
I N FO RMAT I O N
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 4
Flash memory Block Diagram . . . . . . . . . . . . . . . 5
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 6
Special Package Handling Instructions .................................... 6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
MCP Device Bus Operations . . . . . . . . . . . . . . . . . 8
Requirements for Reading Array Data ................................... 10
Writing Commands/Command Sequences ............................ 10
Accelerated Program Operation .......................................... 10
Autoselect Functions ........................................................... 10
Simultaneous Read/Write Operations with Zero Latency ....... 10
Automatic Sleep Mode ........................................................... 11
RESET#: Hardware Reset Pin ............................................... 11
Output Disable Mode .............................................................. 11
Table 2. Am29DL640H Sector Architecture ....................................11
Table 3. Bank Address ....................................................................14
Table 4. SecSi
™ Sector Addresses ...............................................14
Table 5. Am29DL640H Boot Sector/Sector Block Addresses for Pro-
tection/Unprotection ........................................................................15
Write Protect (WP#) ................................................................ 16
Table 6. WP#/ACC Modes ..............................................................16
Temporary Sector Unprotect .................................................. 16
Figure 1. Temporary Sector Unprotect Operation........................... 16
Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 17
SecSi™ (Secured Silicon) Sector
Flash Memory Region ............................................................ 18
Figure 3. SecSi Sector Protect Verify.............................................. 19
Hardware Data Protection ...................................................... 19
Low V
CC Write Inhibit ........................................................... 19
Write Pulse “Glitch” Protection ............................................ 19
Logical Inhibit ...................................................................... 19
Power-Up Write Inhibit ......................................................... 19
Common Flash Memory Interface (CFI) . . . . . . . 19
Flash Command Definitions . . . . . . . . . . . . . . . . 23
Reading Array Data ................................................................ 23
Reset Command ..................................................................... 23
Autoselect Command Sequence ............................................ 23
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence .............................................................. 23
Word Program Command Sequence ..................................... 24
Unlock Bypass Command Sequence .................................. 24
Figure 4. Program Operation .......................................................... 25
Chip Erase Command Sequence ........................................... 25
Sector Erase Command Sequence ........................................ 25
Erase Suspend/Erase Resume Commands ........................... 26
Figure 5. Erase Operation............................................................... 26
Flash Write Operation Status . . . . . . . . . . . . . . . . 28
DQ7: Data# Polling ................................................................. 28
Figure 6. Data# Polling Algorithm ................................................... 28
DQ6: Toggle Bit I .................................................................... 29
Figure 7. Toggle Bit Algorithm......................................................... 29
DQ2: Toggle Bit II ................................................................... 30
Reading Toggle Bits DQ6/DQ2 ............................................... 30
DQ5: Exceeded Timing Limits ................................................ 30
DQ3: Sector Erase Timer ....................................................... 30
Table 12. Write Operation Status ................................................... 31
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 32
Figure 8. Maximum Negative Overshoot Waveform ...................... 32
Figure 9. Maximum Positive Overshoot Waveform........................ 32
Flash DC Characteristics . . . . . . . . . . . . . . . . . . 33
CMOS Compatible .................................................................. 33
Figure 10. I
CC1 Current vs. Time (Showing Active and
Automatic Sleep Currents) ............................................................. 34
Figure 11. Typical I
CC1 vs. Frequency ............................................ 34
Pseudo SRAM DC and
Operating Characteristics . . . . . . . . . . . . . . . . . . 35
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 12. Test Setup.................................................................... 36
Figure 13. Input Waveforms and Measurement Levels ................. 36
Figure 14. ...................................................................................... 36
Read-Only Operations ........................................................... 37
Figure 15. Read Operation Timings ............................................... 37
Hardware Reset (RESET#) .................................................... 38
Figure 16. Reset Timings ............................................................... 38
Erase and Program Operations .............................................. 39
Figure 17. Program Operation Timings.......................................... 40
Figure 18. Accelerated Program Timing Diagram .......................... 40
Figure 19. Chip/Sector Erase Operation Timings .......................... 41
Figure 20. Back-to-back Read/Write Cycle Timings ...................... 42
Figure 21. Data# Polling Timings (During Embedded Algorithms). 42
Figure 22. Toggle Bit Timings (During Embedded Algorithms)...... 43
Figure 23. DQ2 vs. DQ6................................................................. 43
Temporary Sector Unprotect .................................................. 44
Figure 24. Temporary Sector Unprotect Timing Diagram .............. 44
Figure 25. Sector/Sector Block Protect and
Unprotect Timing Diagram ............................................................. 45
Alternate CE#f Controlled Erase and Program Operations .... 46
Figure 26. Flash Alternate CE#f Controlled Write (Erase/Program)
Operation Timings.......................................................................... 47
Pseudo SRAM AC Characteristics . . . . . . . . . . . 48
Power Up Time ....................................................................... 48
Read Cycle ............................................................................. 48
Figure 27. Pseudo SRAM Read Cycle—Address Controlled......... 48
Figure 28. Pseudo SRAM Read Cycle........................................... 49
Write Cycle ............................................................................. 50
Figure 29. Pseudo SRAM Write Cycle—WE# Control ................... 50
Figure 30. Pseudo SRAM Write Cycle—CE1#s Control ................ 51
Figure 31. Pseudo SRAM Write Cycle—
UB#s and LB#s Control.................................................................. 52
Flash Erase And Programming Performance . . 53
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 53
Package Pin Capacitance. . . . . . . . . . . . . . . . . . . 53
Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 53
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 54
FLJ073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm .............. 54
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 55


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