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ISL5314IN датащи(PDF) 6 Page - Intersil Corporation

номер детали ISL5314IN
подробное описание детали  Direct Digital Synthesizer
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производитель  INTERSIL [Intersil Corporation]
домашняя страница  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL5314IN датащи(HTML) 6 Page - Intersil Corporation

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6
If M-ary FSK is required (more than two frequencies), the user
will have to continually reprogram the center frequency register.
The maximum write rate to the same parallel register is the
lesser of 50MSPS or fCLK/2. One WR clock cycle is required for
every register updated. The maximum possible rate occurs if
the user only needs to change eight bits (one register). For M-
ary FSK, the output frequency rate of change is
M-ary FSK Rate = WR / REG,
where REG = quantity of registers being written and WR =
write rate.
PSK Modulation
Binary or quadrature phase shift keying (PSK) can be done
by using the phase pins, PH0 and PH1. The change in
phase can be pipelined such that the PH pins can be toggled
at a rate up to
PHMAX = fCLK/2,
where fCLK is the frequency of the master CLK.
Quadrature Local Oscillators
Two ISL5314s can be used as sine/cosine generators for
quadrature local oscillator applications. It is important to note
that the phase accumulator feedback needs to be zeroed in
both devices if it is desired that both DDSs restart with a
known phase, which is determined by the use of the phase
control pins, PH1 and PH0. To zero the phase accumulator,
pull bit 5 of address 13 low and then high again at the same
time in both devices.
Squarewave Clock Source
The on-chip comparator can be used to generate a square
wave. The analog output is filtered and then fed into the
comparator input. Because the analog output is a sampled-
waveform, a high DAC output frequency (relative to the clock
rate) creates large amplitude steps in the sampled
waveform. These steps have to be smoothed with a lowpass
filter in order for the comparator to operate properly,
otherwise the zero-order hold nature of the sampled analog
output could possibly hold at the comparator’s trigger point
temporarily causing the comparator to toggle unexpectedly.
For this reason, it is very important that a lowpass filter be
used on the analog output prior to the input of the
comparator. The user can set one input to the comparator at
a DC reference point (typically the mid-point of the filtered
signal) and feed the filtered analog output into the other
input. See Figure 2 for an example of a square wave circuit
using this method. Since IOUTA and IOUTB are differential,
the mid-point between the 10k resistors will always be the
average value of each signal. The large resistors have to be
used so that the parallel resistance of the intended load and
the extra load of the averaging circuit yields a negligible
effect on the intended load. The average value is used as the
reference voltage for one input to the comparator, with a
capacitor to filter off any high frequency noise. The other
comparator input is connected to the lowpass filter output. It
is important that both IOUTA and IOUTB are equally loaded
so that each generates the same amplitude and therefore
has the same average value.
The user can filter both IOUTA and IOUTB and feed them
differentially into the comparator. It is difficult to perfectly
match the differential option, so the single-ended option is
recommended. The jitter of the comparator is typically 500ps
peak to peak. The actual jitter achieved is partially
dependent on the quality of the signal at the comparator
input, which is dictated by the amount of oversampling of the
analog output and the quality of the lowpass filter.
The user also has the option to evaluate the comparator
circuit in Figure 2 with lower output current in order to save
power consumption in the ISL5314. The DAC output current
can be set to 5 or 10mA instead of 20mA and evaluated to
determine if the comparator performance is still suitable for
the application. Since the output current is derived from the
+5V analog supply, reducing the output from 20mA to 10mA
saves approximately 50mW of power. The recommended
minimum amplitude of the comparator input is 100mV, so
operation of the analog outputs with less than 20mA of
output current should be possible with appropriate resistive
loading (for example, 5mA into a 50
Ω load provides 250mV
of amplitude).
If needed, series resistance on the comparator output can
be used to reduce overshoot and/or ringing. The comparator
can be used to drive a 50
Ω load.
PIN 18
PIN 17
>10k
ISL5314
100
50
FIGURE 2. SQUAREWAVE GENERATION USING THE
ON-CHIP COMPARATOR
IOUTA
IOUTB
>10k
100
LPF (100
Ω)
PIN 23
PIN 22
IN+
IN-
PIN 10
COMPOUT
>1nF
COMPARATOR INPUTS
(TYP 20-40MHz)
ISL5314


Аналогичный номер детали - ISL5314IN

производительномер деталидатащиподробное описание детали
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