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CDC706PWRG4 датащи(PDF) 7 Page - Texas Instruments |
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CDC706PWRG4 датащи(HTML) 7 Page - Texas Instruments |
7 / 41 page www.ti.com CDC706 SCAS829A – SEPTEMBER 2006 – REVISED MARCH 2007 DEVICE CHARACTERISTICS (continued) over recommended operating free-air temperature range and test load (unless otherwise noted), see Figure 1 PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT fOUT = 50 MHz 60 90 1 PLL, 1 Output fOUT = 245.76 MHz 55 80 tjit(per) Peak-to-peak period jitter (5)(6) ps fOUT = 50 MHz 145 180 3 PLLs, 3 Outputs fOUT = 245.76 MHz 70 105 Output skew (see (7) and Table 5) 1.6-ns rise/fall time at tsk(o) 200 ps f(VCO) = 150 MHz, Pdiv = 3 odc Output duty cycle(8) f(VCO) = 100 MHz, Pdiv = 1 45% 55% LVCMOS PARAMETER FOR VCCOUT = 2.5-V Mode(9) VCCOUT = 2.3 V, IOH = 0.1 mA 2.2 VOH LVCMOS high-level output voltage VCCOUT = 2.3 V, IOH = –3 mA 1.7 V VCCOUT = 2.3 V, IOH = –4 mA 1.5 VCCOUT = 2.3 V, IOL = 0.1 mA 0.1 VOL LVCMOS low-level output voltage VCCOUT = 2.3 V, IOL = 3 mA 0.5 V VCCOUT = 2.3 V, IOL = 4 mA 0.85 All PLL bypass 9 tPLH, Propagation delay ns tPHL VCO Bypass 11 Rise and fall time for output tr0/tf0 VCCOUT = 2.5 V (20%–80%) 2 3.9 5.6 ns slew rate 0 Rise and fall time for output tr1/tf1 VCCOUT = 2.5 V (20%–80%) 1.8 2.9 4.4 ns slew rate 1 Rise and fall time for output tr2/tf2 VCCOUT = 2.5 V (20%–80%) 1.3 2 3.2 ns slew rate 2 Rise and fall time for output tr3/tf3 VCCOUT = 2.5 V (20%–80%) 0.4 0.8 1.1 ns slew rate 3 (default configuration) fOUT = 50 MHz 60 105 1 PLL, 1 Output fOUT = 245.76 MHz 50 85 tjit(cc) Cycle-to-cycle jitter (10)(11) ps fOUT = 50 MHz 130 160 3 PLLs, 3 Outputs fOUT = 245.76 MHz 60 95 fOUT = 50 MHz 65 110 1 PLL, 1 Output fOUT = 245.76 MHz 60 90 tjit(per) Peak-to-peak period jitter (10)(11) ps fOUT = 50 MHz 145 180 3 PLLs, 3 Outputs fOUT = 245.76 MHz 70 105 Output skew (see (12) and Table 5) 2-ns rise/fall time at tsk(o) 250 ps f(VCO) = 150 MHz, Pdiv = 3 odc Output duty cycle(13) f(VCO) = 100 MHz, Pdiv = 1 45% 55% SMBus PARAMETER SCLK and SDATA input clamp VIK VCC = 3 V, II = –18 mA –1.2 V voltage II SCLK and SDATA input current VI = 0 V or VCC, VCC = 3.6 V ±5 µA VIH SCLK input high voltage 2.1 V VIL SCLK input low voltage 0.8 V VOL SDATA low-level output voltage IOL = 4 mA, VCC = 3 V 0.4 V (7) The tsk(o) specification is only valid for equal loading of all outputs. (8) odc depends on output rise and fall time (tr/tf). The data is for normal tr/tf and is valid for both SSC on and off. (9) T here is a limited drive capability at output supply voltage of 2.5 V. For proper termination, see application report SCAA080. (10) 50000 cycles. (11) Jitter depends on configuration. Jitter data is normal tr/tf, input frequency = 3.84 MHz, f(VCO) = 245.76 MHz. (12) The tsk(o) specification is only valid for equal loading of all outputs. (13) odc depends on output rise and fall time (tr/tf). The data is for normal tr/tf and is valid for both SSC on and off. 7 Submit Documentation Feedback |
Аналогичный номер детали - CDC706PWRG4 |
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Аналогичное описание - CDC706PWRG4 |
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