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AD7765 датащи(PDF) 10 Page - Analog Devices

номер детали AD7765
подробное описание детали  24-Bit, 156 kSPS, 112 dB 誇-? ADC with On-Chip Buffers and Serial Interface
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
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AD7765 датащи(HTML) 10 Page - Analog Devices

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AD7765
Rev. 0 | Page 10 of 32
Pin No.
Mnemonic
Description
14
FSI
Frame Sync Input. The status of this pin is checked on the falling edge of SCO. If this pin is low, then the first
data bit is latched in on the next SCO falling edge. See the AD7765 Interface section for further details.
15
SYNC
Synchronization Input. A falling edge on this pin resets the internal filter. This can be used to synchronize
multiple devices in a system. See the Synchronization section for further details.
16
RESET/
PWRDWN
Reset/Powerdown Pin. When a logic low is sensed on this pin, the part is powered down and all internal
circuitry is reset.
19
MCLK
Master Clock Input. A low jitter digital clock must be applied to this pin. The output data rate depends on the
frequency of this clock. See the Clocking the AD7765 section for more details.
18
DEC_RATE
Decimation Rate. This pin selects one of the three decimation rate modes. When 2.5 V is applied to this pin, a
decimation rate of 128× is selected. A decimation rate of 256× is selected by setting the pin to ground.


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