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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TDA2579C датащи(PDF) 6 Page - NXP Semiconductors |
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TDA2579C датащи(HTML) 6 Page - NXP Semiconductors |
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6 / 24 page  January 1994 6 Philips Semiconductors Preliminary specification Synchronization circuit with synchronized vertical divider system for 60 Hz TDA2579C In accordance with the convention for the M system, field one line 1 number 1 starts at the first equalizing pulse, the reset of the divider system is at the start of line 4 for the first field and in the middle of line 265 for the second field. Divider system MODE A: LARGE (SEARCH) WINDOW Divider ratio between 488 and 576. This mode is valid for the following five conditions: 1. Divider is locking to a new transmitter. 2. Divider ratio found, not being within the narrow window limits. 3. Up/down counter value of the divider system operating in the narrow window mode decreases below count 1. 4. External forced setting. This can be achieved by loading pin 18 with a 220 Ω resistor to earth or by connecting a 3.6 V stabistor diode between pin 18 and ground. 5. A vertical sync pulse was detected within the interval provided by reset divider (at 528) and the end of the vertical blanking while the voltage at pin 18 is ≤1.2 V. MODE B: NARROW WINDOW Divider ratio between 522 and 528. The divider system switches over to this mode when the up/down counter has reached its maximum value of 12 approved vertical sync pulses in the large window mode. When count 12 is reached the vertical sync pulse is tested for the standard TV-norm being the divider ratio 525. When this value is valid for the 12th vertical pulse, the up/down counter is reset to 0 and the up/down counter tests for a valid 525 divider ratio. When at the 12th vertical pulse the divider ratio is not equal to n = 525 then the divider system remains in the narrow window mode and remains testing for the standard TV-norm. When the divider operates in this mode and a vertical sync pulse is missing within the window the divider is reset at the end of the window and the counter value is decreased by 1. At a counter value below count 1 the divider system switches over to the large window mode. MODE C: STANDARD TV-NORM Divider ratio 525; fV = 60 Hz. When the up/down counter has reached its maximum value of 12 in the narrow window mode and the divider ratio equals n = 525 the information applied to the up/down counter is changed such that now the standard divider ratio value is tested and the up/down counter is reset to 0. When the up/down counter reaches the value of 14 approved M TV-norm pulses the divider system is changed over to the standard divider ratio mode. In this mode the divider is always reset at the standard value even if the vertical sync pulse is missing. A missed vertical sync pulse decreases the counter value by 1. When the counter reaches the value of 10 the divider system is switched over to the large window mode. The standard TV-norm condition provides maximum protection for video recorders playing tapes with anti-copy guards. MODE D: NO TV TRANSMITTER FOUND At pin 18 the voltage level is less than 1.2 V. In this condition, only noise is present and no vertical sync pulse is detected, the divider is reset to count 528. In this way a stable picture display at normal height is achieved. MODE E: VIDEO TAPE RECORDERS IN FEATURE MODE NTSC (M system) 3-speed video tape recorders It should be noted that some VTRs operating in the picture search mode, generate such distorted pictures that the no TV transmitter detection circuit can be activated as the voltage on pin 18 drops below 1.2 V. This would imply a rolling picture (Mode D). In general VTRs do use a re-inserted vertical pulse in the feature mode. Therefore the divider system has been designed such that the divider is forced to the wide window mode when V18 is below 1.2 V and a vertical sync pulse is detected within the window provided by the reset divider at 528 and the end of the vertical blanking period. General The divider system also generates the anti-top-flutter pulse which inhibits the Phase 1 detector during the vertical sync pulse. The width of this pulse depends on the divider mode. For the divider mode A the start is generated at the reset of the divider. In modes B and C the anti-top-flutter pulse starts at the beginning of the first equalizing pulse sequence. The anti-top-flutter ends after the second equalizing pulse sequence. The vertical blanking pulse is also generated via the divider system. The start is at the reset of the divider while the blanking pulse ends at count 34, the middle of line 21 of field 1 and at the end of line 283 of field 2. The vertical blanking pulse generated at the sandcastle output pin 17 is made by adding the anti-top-flutter pulse and the blanking pulse. In this way the vertical blanking pulse starts at the beginning of the first equalizing pulse when the divider operates in the B or C mode. |
Аналогичный номер детали - TDA2579C |
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Аналогичное описание - TDA2579C |
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