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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TDA4841 датащи(PDF) 8 Page - NXP Semiconductors |
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TDA4841 датащи(HTML) 8 Page - NXP Semiconductors |
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8 / 60 page  1999 Oct 25 8 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors TDA4841PS The resistor RHBUFpar is calculated as the value of RHREF and RHBUF in parallel. The formulae for RHBUF additionally takes into account the voltage swing across this resistor: PLL1 phase detector The phase detector is a standard type using switched current sources, which are independent of the horizontal frequency. It compares the middle of horizontal sync with a fixed point on the oscillator sawtooth voltage. The PLL1 loop filter is connected to HPLL1 (pin 26). See also Section “Horizontal position adjustment and corrections”. Horizontal position adjustment and corrections Via register HPOS the I2C-bus allows a linear adjustment of the relative phase between the horizontal sync and oscillator sawtooth (in PLL1 loop). Once adjusted, the relative phase remains constant over the whole frequency range. Via registers HPARAL and HPINBAL correction of pin unbalance and parallelogram is achieved by modulating the phase between oscillator sawtooth and horizontal flyback (in loop PLL2). If those asymmetric EW corrections are performed in the deflection stage, both registers can be disconnected from horizontal phase via control bit ACD. This does not change the output at pin ASCOR. Horizontal moire cancellation To achieve a cancellation of horizontal moire (also known as ‘video moire’), the horizontal frequency is divided-by-two for a modulation of the horizontal phase via PLL2. The amplitude is controlled by register HMOIRE. To avoid a visible structure on screen the polarity changes with half the vertical frequency. Control bit MOD disables the moire cancellation function. PLL2 phase detector The PLL2 phase detector is similar to the PLL1 detector and compares the line flyback pulse at HFLB (pin 1) with the oscillator sawtooth voltage. The control currents are independent of the horizontal frequency. The PLL2 detector thus compensates for the delay in the external horizontal deflection circuit by adjusting the phase of the HDRV (pin 8) output pulse. R HBUF R HREF R HBUFpar × R HREF R HBUFpar – ---------------------------------------------- 0.8 × = 805 Ω = An external modulation of the PLL2 phase is not allowed, because this would disturb the pre-correction of the H-focus parabola. Soft start and standby If HPLL2 is pulled to ground, either by an external DC current or by resetting the register SOFTST, horizontal output pulses and B+ control driver pulses are inhibited. This means that HDRV (pin 8), BDRV (pin 6), VOUT1 (pin 13) and VOUT2 (pin 12) are floating in this state. PLL2 and the frequency-locked loop are disabled, CLBL (pin 16) provides a continuous blanking signal and HUNLOCK (pin 17) is floating. This option can be used for soft start, protection and power-down modes. When the HPLL2 pin is released again, an automatic soft start sequence on the horizontal drive as well as on the B − drive output will be performed (see Fig.22). A soft start can only be performed if the supply voltage for the IC is 8.6 V minimum. The soft start timing is determined by the filter capacitor at HPLL2 (pin 30), which is charged with an constant current during soft start. If the voltage at pin 30 (HPLL2) reaches 1.1 V, the vertical output currents are enabled. At 1.8 V the horizontal driver stage generates very small output pulses. The width of these pulses increases with the voltage at HPLL2 until the final duty cycle is reached. The voltage at HPLL2 increases further and performs a soft start at BDRV (pin 6) as well. After BDRV has reached full duty cycle, the voltage at HPLL2 continues to rise until HPLL2 enters its normal operating range. The internal charge current is now disabled. Finally PLL2 and the frequency-locked loop are activated. If both functions reach normal operation, HUNLOCK (pin 17) switches from the floating status to normal vertical blanking, and continuous blanking at CLBL (pin 16) is removed. Output stage for line drive pulses [HDRV (pin 8)] An open-collector output stage allows direct drive of an inverting driver transistor because of a low saturation voltage of 0.3 V at 20 mA. To protect the line deflection transistor, the output stage is disabled (floating) for low supply voltage at VCC (see Fig.26). The duty cycle of line drive pulses is slightly dependent on the actual horizontal frequency. This ensures optimum drive conditions over the whole frequency range. |
Аналогичный номер детали - TDA4841 |
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Аналогичное описание - TDA4841 |
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