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SI5322 датащи(PDF) 5 Page - Silicon Laboratories |
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SI5322 датащи(HTML) 5 Page - Silicon Laboratories |
5 / 16 page Si5322 Preliminary Rev. 0.47 5 1. Functional Description The Si5322 is a low jitter, precision clock multiplier for high-speed communication systems, including SONET OC-48/OC-192, Ethernet, and Fibre Channel. The Si5322 accepts dual clock inputs ranging from 19.44 to 707 MHz and generates two frequency-multiplied clock outputs ranging from 19.44 to 1050 MHz. The two input clocks are at the same frequency and the two output clocks are at the same frequency. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, and Fibre Channel rates. In addition to providing clock multiplication in SONET and datacom applications, the Si5322 supports SONET-to-datacom frequency translations. Silicon Laboratories offers a PC-based software utility, DSPLLsim, that can be used to look up valid Si5322 frequency translations. This utility can be downloaded from www.silabs.com/timing. This information is also available in the Any-Rate Precision Clock Family Reference Manual, also available from www.silabs.com/timing. The Si5322 is recommended for applications in which the input clock is relatively low jitter and only clock multiplication is required. The Si5322 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides any-rate frequency synthesis in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The Si5322 PLL loop bandwidth is selectable via the BWSEL[1:0] pins and supports a range from 30 kHz to 1.5 MHz. The DSPLLsim software utility can be used to calculate valid loop bandwidth settings for a given input clock frequency/clock multiplication ratio. The Si5322 monitors all input clocks for loss of signal and provides a LOS alarm when it detects a missing clock. In the case when the input clocks enter alarm conditions, the PLL will freeze the DCO output frequency near its last value to maintain operation with an internal state close to the last valid operating state. The Si5322 has two differential clock outputs. The electrical format of the clock outputs is programmable to support LVPECL, LVDS, CML, or CMOS loads. If not required, the second clock output can be powered down to minimize power consumption. The phase difference between the selected input clock and the output clocks is adjustable in 200 ps increments for system skew control. For system-level debugging, a bypass mode is available which drives the output clock directly from the input clock, bypassing the internal DSPLL. The device is powered by a single 1.8, 2.5, or 3.3 V supply. 1.1. Further Documentation Consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual (FRM) for more detailed information about the Si5322. The FRM can be downloaded from www.silabs.com/timing. Silicon Laboratories has developed a PC-based software utility called DSPLLsim to simplify device configuration, including frequency planning and loop bandwidth selection. This utility can be downloaded from www.silabs.com/timing. |
Аналогичный номер детали - SI5322 |
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Аналогичное описание - SI5322 |
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