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TDA8002B датащи(PDF) 8 Page - NXP Semiconductors

номер детали TDA8002B
подробное описание детали  IC card interface
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производитель  PHILIPS [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

TDA8002B датащи(HTML) 8 Page - NXP Semiconductors

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1997 Nov 04
8
Philips Semiconductors
Product specification
IC card interface
TDA8002
Table 1
Clock circuitry definition
Notes
1. X = don’t care.
2. In low-power mode.
3. fint = 32 kHz in low-power mode.
MODE
CLKSEL
CLKDIV1
CLKDIV2
FREQUENCY
OF CLK
FREQUENCY
OF CLKOUT
HIGH
LOW
HIGH
LOW
1
2fint
1
2fint
HIGH
LOW
LOW
LOW
1
4fxtal
fxtal
HIGH
LOW
LOW
HIGH
1
2fxtal
fxtal
HIGH
LOW
HIGH
HIGH
STOP LOW
fxtal
HIGH
HIGH
X(1)
X(1)
STROBE
fxtal
LOW(2)
X(1)
X(1)
X(1)
STOP LOW
1
2fint(3)
I/O circuitry
The three I/O transceivers are identical. The state is HIGH
for all I/O pins (i.e. I/O, I/OUC, AUX1, AUX1UC, AUX2 and
AUX2UC). Pin I/O is referenced to VCC and pin I/OUC to
VDD, thus ensuring proper operation in case VCC ≠ VDD.
The first side on which a falling edge is detected becomes
a master (input). An anti-latch circuitry first disables the
detection of the falling edge on the other side, which
becomes slave (output).
After a delay time td (about 50 ns), the logic 0 present on
the master side is transferred on the slave side.
When the input is back to HIGH level, a current booster is
turned on during the delay td on the output side and then
both sides are back to their idle state, ready to detect the
next logic 0 on any side.
In case of a conflict, both lines may remain LOW until the
software enables the lines to be HIGH. The anti-latch
circuitry ensures that the lines do not remain LOW if both
sides return HIGH, regardless of the prior conditions.
The maximum frequency on the lines is approximately
1 MHz.
Fig.6 Master and slave signals.
handbook, full pagewidth
td
MGD703
td
td
I/O
I/OUC
conflict
idle


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