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TDA8358 датащи(PDF) 7 Page - NXP Semiconductors

номер детали TDA8358
подробное описание детали  Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier
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производитель  PHILIPS [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

TDA8358 датащи(HTML) 7 Page - NXP Semiconductors

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1999 Dec 22
7
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier
TDA8358J
CHARACTERISTICS
VP = 12 V; VFB = 45 V; fvert = 50 Hz; VI(bias) = 880 mV; Tamb =25 °C; measured in test circuit of Fig.3; unless otherwise
specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VP
operating supply voltage
7.5
12
18
V
VFB
flyback supply voltage
note 1
2VP
45
66
V
Iq(P)(av)
average quiescent supply current
during scan
10
15
mA
Iq(P)
quiescent supply current
no signal; no load
55
75
mA
Iq(FB)(av)
average quiescent flyback supply
current
during scan
−−
10
mA
Inputs A and B
Vi(dif)(p-p)
differential input voltage
(peak-to-peak value)
note 2
1000
1500
mV
VI(bias)
input bias voltage
note 2
100
880
1600
mV
II(bias)
input bias current
25
35
µA
Outputs A and B
Vloss(1)
voltage loss first scan part
note 3
Io = 1.1 A
−−
4.5
V
Io = 1.6 A
−−
6.6
V
Vloss(2)
voltage loss second scan part
note 4
Io = −1.1 A
−−
3.3
V
Io = −1.6 A
−−
4.8
V
Io(p-p)
output current (peak-to-peak value)
−−
3.2
A
LE
linearity error
Io(p-p) = 3.2 A; notes 5 and 6
adjacent blocks
12%
non adjacent blocks
13%
Voffset
offset voltage
across RM; Vi(dif) =0V
VI(bias) = 200 mV
−−±15
mV
VI(bias) =1V
−−±20
mV
∆V
offset(T)
offset voltage variation with
temperature
across RM; Vi(dif) =0V
−−
40
µV/K
VO
DC output voltage
Vi(dif) =0V
0.5VP
V
Gv(ol)
open-loop voltage gain
notes 7 and 8
60
dB
f−3dB(h)
high
−3 dB cut-off frequency
open-loop
1
kHz
Gv
voltage gain
note 9
1
∆G
v(T)
voltage gain variation with
temperature
−−
10−4
K−1
PSRR
power supply rejection ratio
note 10
80
90
dB


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