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STSLVDSP27 датащи(PDF) 5 Page - STMicroelectronics |
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STSLVDSP27 датащи(HTML) 5 Page - STMicroelectronics |
5 / 23 page STSLVDSP27 Pin configuration 5/23 Note: n:0..1; Z = High Impedance, X = Don’t care Note: n:0..1; Z = High Impedance, X = Don’t care Table 2. Truth table (bypass functionality: DIN0 => DOUT, CLKIN => CLKOUT; main chip Enable(1) functionality) Controls Input Differential outputs EN BYP DV0 DV1 DIN0 DIN1-7 CLKIN DOUT+ DOUT- CLKOUT+ CLKOUT- L X X X X X X ZZZZ HH X X L X L L H L H HH X X L X H L H H L HH X X H X L H L L H HH X X H X H H L H L 1. All differential outputs are put in high impedance vs gnd only; the internal DPLL circuit is put in shutdown mode to obtain minimum power consumption. Table 3. Truth table (data valid functionality) Controls Input Differential outputs EN BYP DV0(1) DV1(1) DIN0 DIN1-7 CLKIN DOUT+ DOUT- CLKOUT+ CLKOUT- HL L X X X X H L H L HL X L X X X H L H L 1. An AND gate is designed on Data Valid Inputs (DV0, DV1) to enable the standard functionality; only when the DV0=DV1="H" the device will work according to description in main page |
Аналогичный номер детали - STSLVDSP27 |
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Аналогичное описание - STSLVDSP27 |
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