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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMP102AIDRLR датащи(PDF) 10 Page - Burr-Brown (TI) |
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TMP102AIDRLR датащи(HTML) 10 Page - Burr-Brown (TI) |
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10 / 19 page  www.ti.com SERIAL INTERFACE SERIAL BUS ADDRESS SLAVE MODE OPERATIONS Slave Receiver Mode: WRITING/READING OPERATION Slave Transmitter Mode: TMP102 SBOS397 – AUGUST 2007 Register. This action is accomplished by issuing a slave address byte with the R/W bit low, followed by The TMP102 operates as a slave device only on the the Pointer Register byte. No additional data are two-wire bus and SMBus. Connections to the bus required. The master can then generate a START are made via the open-drain I/O lines SDA and SCL. condition and send the slave address byte with the The SDA and SCL pins feature integrated spike R/W bit high to initiate the read command. See suppression filters and Schmitt triggers to minimize Figure 14 for details of this sequence. If repeated the effects of input spikes and bus noise. The reads from the same register are desired, it is not TMP102 supports the transmission protocol for both necessary to continually send the Pointer Register fast (1kHz to 400kHz) and high-speed (1kHz to bytes, because the TMP102 remembers the Pointer 3.4MHz) modes. All data bytes are transmitted MSB Register value until it is changed by the next write first. operation. Note that register bytes are sent with the most significant byte first, followed by the least significant To communicate with the TMP102, the master must byte. first address slave devices via a slave address byte. The slave address byte consists of seven address bits, and a direction bit indicating the intent of executing a read or write operation. The TMP102 can operate as a slave receiver or slave transmitter. As a slave device, the TMP102 The TMP102 features an address pin to allow up to never drives the SCL line. four devices to be addressed on a single bus. Table 12 describes the pin logic levels used to properly connect up to four devices. The first byte transmitted by the master is the slave Table 12. Address Pin and Slave Addresses address, with the R/W bit low. The TMP102 then acknowledges reception of a valid address. The next DEVICE TWO-WIRE A0 PIN CONNECTION byte transmitted by the master is the Pointer ADDRESS Register. The TMP102 then acknowledges reception 1001000 Ground of the Pointer Register byte. The next byte or bytes 1001001 V+ are written to the register addressed by the Pointer 1001010 SDA Register. The TMP102 acknowledges reception of each data byte. The master can terminate data 1001011 SCL transfer by generating a START or STOP condition. Accessing a particular register on the TMP102 is The first byte transmitted by the master is the slave accomplished by writing the appropriate value to the address, with the R/W bit high. The slave Pointer Register. The value for the Pointer Register acknowledges reception of a valid slave address. is the first byte transferred after the slave address The next byte is transmitted by the slave and is the byte with the R/W bit low. Every write operation to most significant byte of the register indicated by the the TMP102 requires a value for the Pointer Register Pointer Register. The master acknowledges (see Figure 13). reception of the data byte. The next byte transmitted When reading from the TMP102, the last value by the slave is the least significant byte. The master stored in the Pointer Register by a write operation is acknowledges reception of the data byte. The master used to determine which register is read by a read can terminate data transfer by generating a operation. To change the register pointer for a read Not-Acknowledge on reception of any data byte, or operation, a new value must be written to the Pointer generating a START or STOP condition. 10 Submit Documentation Feedback |
Аналогичный номер детали - TMP102AIDRLR |
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Аналогичное описание - TMP102AIDRLR |
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