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CDB42448 датащи(PDF) 4 Page - Cirrus Logic |
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CDB42448 датащи(HTML) 4 Page - Cirrus Logic |
4 / 64 page 4 DS648F2 CS42448 6.16 MUTEC Pin Control (Address 1Bh) .............................................................................................. 52 6.17 MUTEC Polarity Select (MCPOLARITY) ...................................................................................... 52 6.18 MUTE CONTROL ACTIVE (MUTEC ACTIVE) ............................................................................. 52 7. EXTERNAL FILTERS............................................................................................................................ 53 7.1 ADC Input Filter .............................................................................................................................. 53 7.1.1 Passive Input Filter ................................................................................................................ 54 7.1.2 Passive Input Filter w/Attenuation ......................................................................................... 54 7.2 DAC Output Filter ........................................................................................................................... 56 8. ADC FILTER PLOTS............................................................................................................................. 57 9. DAC FILTER PLOTS............................................................................................................................. 59 10. PARAMETER DEFINITIONS............................................................................................................... 61 11. REFERENCES..................................................................................................................................... 62 12. PACKAGE INFORMATION................................................................................................................. 63 12.1 Thermal Characteristics ............................................................................................................... 63 13. ORDERING INFORMATION ............................................................................................................... 64 14. REVISION HISTORY ........................................................................................................................... 64 LIST OF FIGURES Figure 1.Typical Connection Diagram ......................................................................................................... 9 Figure 2.Output Test Circuit for Maximum Load ....................................................................................... 16 Figure 3.Maximum Loading ....................................................................................................................... 16 Figure 4.Serial Audio Interface Slave Mode Timing .................................................................................. 18 Figure 5.TDM Serial Audio Interface Timing ............................................................................................. 18 Figure 6.Serial Audio Interface Master Mode Timing ................................................................................ 19 Figure 7.Serial Audio Interface Slave Mode Timing .................................................................................. 20 Figure 8.Control Port Timing - I²C Format ................................................................................................. 21 Figure 9.Control Port Timing - SPI Format ................................................................................................ 22 Figure 10.Full-Scale Input ......................................................................................................................... 25 Figure 11.ADC3 Input Topology ................................................................................................................ 25 Figure 12.Audio Output Initialization Flow Chart ....................................................................................... 27 Figure 13.Full-Scale Output ...................................................................................................................... 29 Figure 14.De-Emphasis Curve .................................................................................................................. 30 Figure 15.I²S Format ................................................................................................................................. 32 Figure 16.Left Justified Format ................................................................................................................. 32 Figure 17.Right Justified Format ............................................................................................................... 32 Figure 18.One-Line Mode #1 Format ........................................................................................................ 32 Figure 19.One Line Mode #2 Format ........................................................................................................ 33 Figure 20.TDM Format .............................................................................................................................. 33 Figure 21.AUX I²S Format ......................................................................................................................... 34 Figure 22.AUX Left-Justified Format ......................................................................................................... 35 Figure 23.Control Port Timing in SPI Mode .............................................................................................. 36 Figure 24.Control Port Timing, I²C Write ................................................................................................... 36 Figure 25.Control Port Timing, I²C Read ................................................................................................... 37 Figure 26.Single to Differential Active Input Filter ..................................................................................... 53 Figure 27.Single-Ended Active Input Filter ................................................................................................ 53 Figure 28.Passive Input Filter ................................................................................................................... 54 Figure 29.Passive Input Filter w/Attenuation ............................................................................................. 55 Figure 30.Active Analog Output Filter ....................................................................................................... 56 Figure 31.Passive Analog Output Filter .................................................................................................... 56 Figure 32.SSM Stopband Rejection .......................................................................................................... 57 Figure 33.SSM Transition Band ................................................................................................................ 57 Figure 34.SSM Transition Band (Detail) ................................................................................................... 57 Figure 35.SSM Passband Ripple .............................................................................................................. 57 |
Аналогичный номер детали - CDB42448 |
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Аналогичное описание - CDB42448 |
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