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CS5560 датащи(PDF) 9 Page - Cirrus Logic |
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CS5560 датащи(HTML) 9 Page - Cirrus Logic |
9 / 32 page CS5560 DS713A5 9 7/31/07 SWITCHING CHARACTERISTICS (CONTINUED) TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic 0 = 0V; Logic 1 = VD+; CL = 15 pF. 16. SDO will be high impedance when CS is high. In some systems it may require a pull-down resistor. Parameter Symbol Min Typ Max Unit Serial Port Timing in SEC Mode (SMODE = VLR) SCLK(in) Pulse Width (High) - 30 - - ns SCLK(in) Pulse Width (Low) - 30 - - ns CS hold time (high) after RDY falling t15 10 - - ns CS hold time (high) after SCLK rising t16 10 - - ns CS low to SDO out of Hi-Z (Note 16) t17 -10 - ns Data hold time after SCLK rising t18 -10 - ns Data setup time before SCLK rising t19 10 - - ns CS hold time (low) after SCLK rising t20 10 - - ns RDY rising after SCLK falling t21 -10 - ns MCLK SCLK(i) SDO CS RDY LSB MSB t19 t18 t20 t17 t16 t15 t21 Figure 3. SEC Mode - Read Timing (Not to Scale) |
Аналогичный номер детали - CS5560 |
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Аналогичное описание - CS5560 |
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