поискавой системы для электроныых деталей |
|
SI5325C-B-GM датащи(PDF) 8 Page - Silicon Laboratories |
|
SI5325C-B-GM датащи(HTML) 8 Page - Silicon Laboratories |
8 / 14 page Si5325 8 Preliminary Rev. 0.26 22 SCL I LVCMOS Serial Clock/Serial Clock. This pin functions as the serial clock input for both SPI and I2C modes. 23 SDA_SDO I/O LVCMOS Serial Data. In I2C control mode (CMODE = 0), this pin functions as the bidirectional serial data port. In SPI control mode (CMODE = 1), this pin functions as the serial data output. 25 24 A1 A0 ILVCMOS Serial Port Address. In I2C control mode (CMODE = 0), these pins function as hardware controlled address bits. In SPI control mode (CMODE = 1), these pins are ignored. 26 A2_SS ILVCMOS Serial Port Address/Slave Select. In I2C control mode (CMODE = 0), this pin functions as a hardware controlled address bit. In SPI control mode (CMODE = 1), this pin functions as the slave select input. 27 SDI I LVCMOS Serial Data In. In I2C control mode (CMODE = 0), this pin is ignored. In SPI control mode (CMODE = 1), this pin functions as the serial data input. 29 28 CKOUT1– CKOUT1+ OMulti Output Clock 1. Differential output clock with a frequency range of 10 MHz to 1.4175 GHz. Output signal format is selected by SFOUT1_REG register bits. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS for- mat, both output pins drive identical single-ended clock out- puts. 34 35 CKOUT2– CKOUT2+ OMulti Output Clock 2. Differential output clock with a frequency range of 10 MHz to 1.4175 GHz. Output signal format is selected by SFOUT2_REG register bits. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS for- mat, both output pins drive identical single-ended clock out- puts. 36 CMODE I LVCMOS Control Mode. Selects I2C or SPI control mode for the Si5325. 0 = I2C Control Mode. 1 = SPI Control Mode. GND PAD GND GND Supply Ground Pad. The ground pad must provide a low thermal and electrical impedance to a ground plane. Table 3. Si5325 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level Description Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5325 Register Map. |
Аналогичный номер детали - SI5325C-B-GM |
|
Аналогичное описание - SI5325C-B-GM |
|
|
ссылки URL |
Конфиденциальность |
ALLDATASHEETRU.COM |
Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |