Si5368

Preliminary Rev. 0.3

3

Output Clocks (CKOUT1, CKOUT2, CKOUT3, CKOUT4, CKOUT5/FS_OUT)

Common Mode

LVPECL

100

Ω load

line-to-line

—

V

Differential Output Swing

1.1

—

1.9

Single Ended Output Swing

0.5

—

0.93

Vpp

PLL Performance

Jitter Generation

LVPECL output format

50 kHz–80 MHz

—0.3

TBD

ps rms

12 kHz–20 MHz

—

0.3

TBD

ps rms

Jitter Transfer

—0.05

0.1

dB

External Reference Jitter

Transfer

—TBD

TBD

dB

Phase Noise

100 Hz offset

—

TBD

TBD

dBc/Hz

1 kHz offset

—

TBD

TBD

dBc/Hz

10 kHz offset

—

TBD

TBD

dBc/Hz

100 kHz offset

—

TBD

TBD

dBc/Hz

1 MHz offset

—

TBD

TBD

dBc/Hz

Subharmonic Noise

—

TBD

TBD

dBc

Spurious Noise

Max spur @ n x F3

(n > 1, n x F3 < 100 MHz)

—

TBD

TBD

dBc

Package

Thermal Resistance Junction

to Ambient

Still Air

—

40

—

ºC/W

Table 1. Performance Specifications (Continued)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision