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CAT25C64LI-GT3 датащи(PDF) 5 Page - Catalyst Semiconductor

номер детали CAT25C64LI-GT3
подробное описание детали  64K-Bit SPI Serial CMOS EEPROM
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производитель  CATALYST [Catalyst Semiconductor]
домашняя страница  http://www.catalyst-semiconductor.com
Logo CATALYST - Catalyst Semiconductor

CAT25C64LI-GT3 датащи(HTML) 5 Page - Catalyst Semiconductor

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CAT25C64
Doc. No. 1112, Rev. B
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Protected
Unprotected
Status
WPEN
WP
WP
WP
WP
WP
WEL
Blocks
Blocks
Register
0
X
0
Protected
Protected
Protected
0
X
1
Protected
Writable
Writable
1
Low
0
Protected
Protected
Protected
1
Low
1
Protected
Writable
Protected
X
High
0
Protected
Protected
Protected
X
High
1
Protected
Writable
Writable
WRITE PROTECT ENABLE OPERATION
the communication between the microcontroller and the
25C64. Opcodes, byte addresses, or data present on
the SI pin are latched on the rising edge of the SCK. Data
on the SO pin is updated on the falling edge of the SCK.
CS
CS
CS
CS
CS: Chip Select
CS is the Chip select pin. CS low enables the CAT25C64
and
CS high disables the CAT25C64. CS high takes the
SO output pin to high impedance and forces the devices
into a Standby Mode (unless an internal write operation
is underway). The CAT25C64 draws ZERO current in
the Standby mode. A high to low transition on
CS is
required prior to any sequence being initiated. A low to
high transition on
CS after a valid write sequence is what
initiates an internal write cycle.
WP
WP
WP
WP
WP: Write Protect
WP is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When
WP is tied low and the WPEN bit in the status
register is set to “1”, all write operations to the status
register are inhibited.
WP going low while CS is still low
will interrupt a write to the status register. If the internal
write cycle has already been initiated,
WP going low will
have no effect on any write operation to the status
register. The
WP pin function is blocked when the WPEN
bit is set to 0.
HOLD
HOLD
HOLD
HOLD
HOLD: Hold
The
HOLD pin is used to pause transmission to the
CAT25C64 while in the middle of a serial sequence
without having to re-transmit entire sequence at a later
time. To pause,
HOLD must be brought low while SCK
is low. The SO pin is in a high impedance state during the
time the part is paused, and transitions on the SI pins will
be ignored. To resume communication,
HOLD is brought
high, while SCK is low.
(HOLD should be held high any
time this function is not being used.)
HOLD may be tied
high directly to Vcc or tied to Vcc through a resistor.
Figure 9 illustrates hold timing sequence.
76543210
WPEN
X
X
X
BP1
BP0
WEL
RDY
STATUS REGISTER
Status Register Bits
Array Address
Protection
BP1
BP0
Protected
0
0
None
No Protection
0
1
1800-1FFF
Quarter Array Protection
1
0
1000-1FFF
Half Array Protection
1
1
0000-1FFF
Full Array Protection
BLOCK PROTECTION BITS


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