REV. A

–8–

AD9945

INTERNAL REGISTER DESCRIPTION

Table I. Internal Register Map

Register

Address Bits

Name

A2

A1

A0

Data Bits

Function

Operation

0

0

0

D0

Software Reset (0 = Normal Operation, 1 = Reset all registers to default)

D2, D1

Power-Down Modes (00 = Normal Power, 01 = Standby, 10 = Total Shutdown)

D3

OB Clamp Disable (0 = Clamp ON, 1 = Clamp OFF)

D5, D4

Test Mode. Should always be set to 00.

D6

PBLK Blanking Level (0 = Blank Output to Zero, 1 = Blank to OB Clamp Level)

D8, D7

Test Mode 1. Should always be set to 00.

D11 to D9

Test Mode 2. Should always be set to 000.

Control

0

0

1

D0

SHP/SHD Input Polarity (0 = Active Low, 1 = Active High)

D1

DATACLK Input Polarity (0 = Active Low, 1 = Active High)

D2

CLPOB Input Polarity (0 = Active Low, 1 = Active High)

D3

PBLK Input Polarity (0 = Active Low, 1 = Active High)

D4

Three-State Data Outputs (0 = Outputs Active, 1 = Outputs Three-Stated)

D5

Data Output Latching (0 = Latched by DATACLK, 1 = Latch is Transparent)

D6

Data Output Coding (0 = Binary Output, 1 = Gray Code Output)

D11 to D7

Test Mode. Should always be set to 00000.

Clamp Level

0

1

0

D7 to D0

OB Clamp Level (0 = 0 LSB, 255 = 255 LSB)

VGA Gain

0

1

1

D9 to D0

VGA Gain (0 = 6 dB, 1023 = 40 dB)

NOTE: All register values default to 0x000 at power-up except clamp level, which defaults to 128 decimal (128 LSB clamp level).