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ADC10732CIWM датащи(PDF) 7 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
номер детали ADC10732CIWM
подробное описание детали  10-Bit Plus Sign Serial I/O A/D Converters with Mux, Sample/Hold and Reference
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производитель  NSC [National Semiconductor (TI)]
домашняя страница  http://www.national.com
Logo NSC - National Semiconductor (TI)

ADC10732CIWM датащи(HTML) 7 Page - National Semiconductor (TI)

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Electrical Characteristics (Continued)
The following specifications apply for V
+ =AV+ =DV+ = +5.0 V
DC,VREF+ = 2.5 VDC,VREF− = GND, VIN− = 2.5V for Signed
Characteristics, V
IN− = GND for Unsigned Characteristics and fCLK = 2.5 MHz unless otherwise specified. Boldface limits ap-
ply for T
A =TJ =TMIN to TMAX; all other limits TA =TJ = +25˚C. (Notes 8, 9, 10)
Symbol
Parameter
Conditions
Typical
(Note 11)
Limits
(Note 12)
Units
(Limits)
AC CHARACTERISTICS
t
SCS
CS Set-Up Time, Set-Up Time from
Falling Edge of CS to Rising Edge of
Clock
14
30
ns (min)
(1 t
CLK
−14ns)
(1 t
CLK
−30ns)
(max)
t
SDI
DI Set-Up Time, Set-Up Time from
Data Valid on DI to Rising Edge of
Clock
16
25
ns (min)
t
HDI
DI Hold Time, Hold Time of DI Data
from Rising Edge of Clock to Data not
Valid on DI
2
25
ns (min)
t
AT
DO Access Time from Rising Edge of
CLK When CS is “Low” during a
Conversion
30
50
ns (min)
t
AC
DO or SARS Access Time from CS ,
Delay from Falling Edge of CS to Data
Valid on DO or SARS
30
70
ns (max)
t
DSARS
Delay from Rising Edge of Clock to
Falling Edge of SARS when CS is
“Low”
100
200
ns (max)
t
HDO
DO Hold Time, Hold Time of Data on
DO after Falling Edge of Clock
20
35
ns (max)
t
AD
DO Access Time from Clock, Delay
from Falling Edge of Clock to Valid
Data of DO
40
80
ns (max)
t
1H,t0H
Delay from Rising Edge of CS to DO
or SARS TRI-STATE
40
50
ns (max)
t
DCS
Delay from Falling Edge of Clock to
Falling Edge of CS
20
30
ns (min)
t
CS(H)
CS “HIGH” Time for A/D Reset after
Reading of Conversion Result
1 CLK
1 CLK
cycle (min)
t
CS(L)
ADC10731 Minimum CS “Low” Time to
Start a Conversion
1 CLK
1 CLK
cycle (min)
t
SC
Time from End of Conversion to CS
Going “Low”
5 CLK
5 CLK
cycle (min)
t
PD
Delay from Power-Down command to
10% of Operating Current
1µs
t
PC
Delay from Power-Up Command to
Ready to Start a New Conversion
10
µs
C
IN
Capacitance of Logic Inputs
7
pF
C
OUT
Capacitance of Logic Outputs
12
pF
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and
test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
Note 4: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > AV
+ or DV+), the current at that pin should be limited to 30 mA.
The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four.
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, θJA and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is PD =(TJmax −TA)/θJA or the number given In the Absolute Maximum Ratings, whichever is lower. For this device,
TJmax = 150˚C. The typical thermal resistance (θJA) of these Paris when board mounted can be found in the following table:
www.national.com
7


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