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SM79108L25 датащи(PDF) 6 Page - SyncMOS Technologies,Inc

номер детали SM79108L25
подробное описание детали  8 - Bit Micro-controller with 8KB flash & 256 Bytes RAM embedded
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производитель  SYNCMOS [SyncMOS Technologies,Inc]
домашняя страница  http://www.syncmos.com.tw
Logo SYNCMOS - SyncMOS Technologies,Inc

SM79108L25 датащи(HTML) 6 Page - SyncMOS Technologies,Inc

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Specifications subject to change without notice,contact your sales representatives for the most recent information.
6/26
Ver 2.1
SM79108 08/2006
SyncMOS Technologies International. Inc.
SM79108
1. Watch Dog Timer
The Watch Dog Timer (WDT) is a 16-bit free-running counter that generate reset signal if the counter overflows. The WDT is
useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead
loop or runaway. The WDT function can help user software recover from abnormal software condition. The WDT is different
from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by software periodically clearing the
WDT counter. User should check WDR bit of SCONF register whenever unpracticed reset happened
The purpose of the secure procedure is to prevent the WDTC value from being changed when system runaway.
There is a 250KHz RC oscillator embedded in chip. Set WDTE = “1” will enable the RC oscillator and the frequency is inde-
pendent to the system frequency.
To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter starts to count
with the RC oscillator. It will generate a reset signal when overflows. The WDTE bit will be cleared to 0 automatically when
SM79108 been reset, either hardware reset or WDT reset.
To reset the WDT is done by setting 1 to the CLEAR bit of WDTC before the counter overflow. This will clear the content of
the 16-bit counter and let the counter re-start to count from the beginning.
1.1 Watch Dog Timer Registers:
Watch Dog Key Register - (WDTKEY, 97H)
By default, the WDTC is read only. User need to write values 1EH, 0E1H sequentially to the WDTKEY(97H) register to
enable the WDTC write attribute, That is
MOV WDTKEY, # 1EH
MOV WDTKEY, # E1H
When WDTC is set, user need to write another values E1H, 1EH sequentially to the WDTKEY(97H) register to disable the
WDTC write attribute, That is
MOV WDTKEY, # E1H
MOV WDTKEY, # 1EH
Addr
SFR
Reset
7
6
5
4
3
2
1
0
0E2H
LCDB1
00H
SEG2
SEG2
SEG2
SEG2
SEG3
SEG3
SEG3
SEG3
0E3H
LCDB2
00H
SEG4
SEG4
SEG4
SEG4
SEG5
SEG5
SEG5
SEG5
0E4H
LCDB3
00H
SEG6
SEG6
SEG6
SEG6
SEG7
SEG7
SEG7
SEG7
0E5H
LCDB4
00H
SEG8
SEG8
SEG8
SEG8
SEG9
SEG9
SEG9
SEG9
0E6H
LCDB5
00H
SEG10
SEG10
SEG10
SEG10
SEG11
SEG11
SEG11
SEG11
0E7H
LCDB6
00H
SEG12
SEG12
SEG12
SEG12
SEG13
SEG13
SEG13
SEG13
bit-7
bit-0
WDT
KEY7
WDT
KEY6
WDT
KEY5
WDT
KEY4
WDT
KEY3
WDT
KEY2
WDT
KEY1
WDT
KEY0
Read / Write:
W
W
W
W
W
W
W
W
Reset value:
0
0
0
0
0
0
0
0


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