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TC9WMB1AFU датащи(PDF) 5 Page - Toshiba Semiconductor

номер детали TC9WMB1AFU
подробное описание детали  CMOS Digital Integrated Circuits Silicon Monolithic
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производитель  TOSHIBA [Toshiba Semiconductor]
домашняя страница  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TC9WMB1AFU датащи(HTML) 5 Page - Toshiba Semiconductor

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TC9WMB1AFK/FU,TC9WMB2AFK/FU
2007-10-19
5
5. Write Operation
(1)
Byte write
A data is written to the specified address at a byte write operation. After a start condition, a device
address,
W
R/
(
= 0), a word address, and write data are received to the device.
When a stop condition is generated subsequently, write operation starts automatically, rewriting
the data at the specified address with the input data. A next instruction cannot be received while
write operation is in progress. Therefore, no acknowledge signal is returned. After writing the data,
the device automatically enters the standby state.
(2)
Page write
A Data is written up to 8 bytes to the specified page at a page write operation. After a start
condition, a device address,
W
R/
(
= 0), a word address (n), and write data (n) are received to the
device, in the same way as for a byte write operation. Then, write data (n
+ 1) is immediately received
without entering a stop condition, while checking that an acknowledge signal is asserted (0).
The first five bits (W3 to W7) of the word address are the same and the lower three bits (W0 to W2)
are automatically incremented so that up to 8 bytes of data can be written.
When the last address within the page is reached, the lower three bits (W0 to W2) of the word
address are rolled over to the first address of the page. If more than 8 bytes of write data are
transferred, the last 8 bytes are valid.
When a stop condition is generated subsequently, write operation starts automatically, rewriting
the data at the specified addresses with the input data.
Figure 5
SDA LINE
1 0 1 0
0
W
6
W
4
W
5
W
3
W
1
W
2
W
0
D
7
D
6
D
4
D
5
D
3
D
1
D
2
D
0
S
T
A
R
T
M
S
B
DEVICE
ADDRESS
W
R
I
T
E
L
S
B
A
C
K
R
/
W
W
7
WORD
ADDRESS
A
C
K
A
C
K
WRITE
DATA
S
T
O
P
Address
increment
M
S
B
L
S
B
A
2
A
1
A
0
*: Optional for the TC9WMB1A.
*
Figure 6
*: Optional for the TC9WMB1A.
SDA LINE
1 0 1 0
0
W
6
W
4
W
5
W
3
W
1
W
2
W
0
D
7
D
6
D
4
D
5
D
3
D
1
D
2
D
0
D
7
D
6
D
4
D
5
D
3
D
1
D
2
D
0
D
4
D
5
D
3
D
1
D
2
D
0
S
T
A
R
T
M
S
B
DEVICE
ADDRESS
W
R
I
T
E
L
S
B
A
C
K
R
/
W
W
7
WORD
ADDRESS (n)
A
C
K
WRITE
DATA (n)
WRITE
DATA (n
+ 1)
A
C
K
WRITE
DATA (n
+ m)
S
T
O
P
A
C
K
Address
increment
Address
increment
Address
increment
A
2
A
1
A
0
*


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