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TC74HC646AP датащи(PDF) 2 Page - Toshiba Semiconductor |
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TC74HC646AP датащи(HTML) 2 Page - Toshiba Semiconductor |
2 / 8 page TC74HC646AP 2007-10-01 2 IEC Logic Symbol Truth Table G DIR CAB CBA SAB SBA A B Function X (Note) X (Note) X X Inputs Z Inputs Z The output functions of A and B busses are disabled. H X X X X X Both A and B busses are used as inputs to the internal flip-flops. Data on the bus will be stored on the rising edge of the clock. X X (Note) L X Inputs L H Outputs L H The data on the A bus are displayed on the B bus. X (Note) L X L H L H The data on the A bus are displayed on the B bus, and are stored into the A storage flip-flops on the rising edge of CAB. X X (Note) H X X Qn The data in the A storage flip-flops are displayed on the B bus. L H X (Note) H X L H L H The data on the A bus are stored into the A storage flip-flops on the rising edge of CAB, and the stored data propagate directly onto the B bus. X (Note) X (Note) X L Outputs L H Inputs L H The data on the B bus are displayed on the A bus. X (Note) X L L H L H The data on the B bus are displayed on the A bus, and are stored into the B storage flip-flops on the rising edge of CBA. X (Note) X (Note) X H Qn X The data in the B storage flip-flops are displayed on the A bus. L L X (Note) X H L H L H The data on the B bus are stored into the B storage flip-flops on the rising edge of CBA, and the stored data propagate directly onto the A bus. X: Don’t care Qn: The data stored into the internal flip-flops by most recent low to high transition of the clock inputs. Z: High impedance Note: The clocks are not internally gated with either G or DIR. Therefore, data on the A and/or B busses may be clocked into the storage flip-flops at any time. |
Аналогичный номер детали - TC74HC646AP |
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Аналогичное описание - TC74HC646AP |
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