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TC9318AFAG датащи(PDF) 6 Page - Toshiba Semiconductor

номер детали TC9318AFAG
подробное описание детали  Single Chip DTS Microcontroller (DTS-21)
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производитель  TOSHIBA [Toshiba Semiconductor]
домашняя страница  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TC9318AFAG датащи(HTML) 6 Page - Toshiba Semiconductor

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TC9318AFAG/AFBG
2006-07-27
6
Pin No.
Symbol
Pin Name
Function and Operation
Remarks
49
HOLD
HOLD mode control
input
Input pin for request/release HOLD mode.
Normally, this pin is used to input radio mode
selection signals or battery detection signals.
HOLD mode includes CLOCK STOP mode (stops
crystal oscillation) and WAIT mode (halts CPU).
Setting is implemented with the CKSTP instruction
or the WAIT instruction. When the CKSTP
instruction is executed, request/release of the
HOLD mode depends on the internal MODE bit. If
the MODE bit is “0” (MODE-0), executing the
CKSTP instruction while the HOLD pin is at low
level stops the clock generator and the CPU and
changes to memory back-up mode. If the MODE
bit is “1” (MODE-1), executing the CKSTP
instruction enters memory back-up mode
regardless of the level of the HOLD pin. Memory
back-up is released when the
HOLD pin goes
high in MODE-0, or when the level of the
HOLD
pin level in MODE-1.
When memory back-up mode is entered by
executing a WAIT instruction, any change in the
HOLD pin input releases the mode.
In memory back-up mode, current consumption is
low (below 10
µA), and all the output pins (e.g.,
display output, output ports) are automatically set
to low level.
50
IFIN/IN
IF signal input/Input
port
IF counter’s IF signal input pin for counting the IF
signals of the FM and AM bands and detecting the
automatic stop position.
The input frequency is between 0.35~12 MHz (0.2
Vp-p (min)). A built-in input amp and C coupling
allow operation at low-level input.
The IF counter is a 20 bit counter with optional
gate times of 1, 4, 16, and 64 ms. 20 bits of data
can be readily stored in memory.
This input pin can be programmed for use as an
input port (IN port). CMOS input is used when the
pin is set as an IN port.
51
52
DO1/OT
DO2
Phase comparison
output/Output port
Phase comparison
output
PLL’s phase comparison tri-state output pins.
When the programmable counter’s prescaler
output is higher than the reference frequency,
output is at high level. When output is lower than
the reference frequency, output is at low level.
When output equals the reference frequency, high
impedance output is obtained.
Because DO1 and DO2 are output in parallel,
optimal filter constants can be designed for the
FM/VHF and AM bands.
Pin DO1 can be programmed to high impedance
or programmed as an output port (OT). Thus, the
pins can be used to improve lock-up time or used
as output ports.


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