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SM5168CX датащи(PDF) 7 Page - Nippon Precision Circuits Inc |
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SM5168CX датащи(HTML) 7 Page - Nippon Precision Circuits Inc |
7 / 9 page SM5168 series SEIKO NPC CORPORATION —7 SM5168C × series Frequency Dividers The comparator frequency divider (N-counter) and reference frequency divider (R-counter), with 2 sets of comparator frequency divider and reference frequency divider ratios, are set in master-slice. The frequency divider set selected is determined by the state of TR (pin 5). The ratio ranges are the same when TR is HIGH or LOW, and are: I Comparator frequency divider (N-counter) = 272 to 65535 I Reference frequency divider (R-counter) = 5 to 65535 Frequency Divider Switching When switching the frequency dividers using TR, the dividers switch in sync with the R-counter divider signal (FR) and the N-counter divider signal (FV) to minimize any disturbance in the PLL loop. If tF represents the FIN cycle time: t1 = 48tF t2 = (divider ratio when TR = LOW) × tF t3 = (divider ratio when TR = HIGH) × tF If tX represents the XIN cycle time: t1 = 3tX t2 = (divider ratio when TR = LOW) × tX t3 = (divider ratio when TR = HIGH) × tX Both the R-counter and N-counter are configured with presettable counters. The divider outputs (FR and FV) are then input to the phase comparator which performs phase comparison on the falling edge of each signal. The FR/FV signals also function as the R/N-counter preset strobe signals, respectively. Consequently, when the TR signal level switches, the decoder output changes on the first FR/FV (R/N-counter preset strobe) signal and the counters are set in the new frequency dividers on the second FR/FV (R/N-counter preset strobe) signal. Fre- quency division with the new frequency dividers starts on the falling edge of the second FR/FV (R/N-counter preset strobe) signal. The timing in the diagram shows an example when TR goes from LOW to HIGH only, but the timing operation is identical under the reverse transition. The R/N-counters operate with the same timing, although the N- counter has a dual modulus prescaler in the initial-stage which means the HIGH-level pulsewidth of the FV and FR signals is different. t2 FV or FR TR Decoder output TR = LOW frequency divider Counter set signal TR = HIGH divider operation starts t1 t2 t3 TR = HIGH frequency divider TR = LOW frequency divider counter set TR = HIGH frequency divider counter set |
Аналогичный номер детали - SM5168CX |
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Аналогичное описание - SM5168CX |
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