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74VHCT573ATTR датащи(PDF) 1 Page - STMicroelectronics |
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74VHCT573ATTR датащи(HTML) 1 Page - STMicroelectronics |
1 / 10 page 74VHCT573A OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING February 2000 s HIGH SPEED: tPD = 5.4 ns (TYP.) at VCC =5V s LOW POWER DISSIPATION: ICC =4 µA (MAX.) at TA =25 oC s COMPATIBLE WITH TTL OUTPUTS: VIH =2V (MIN), VIL = 0.8V (MAX) s POWER DOWN PROTECTION ON INPUTS & OUTPUTS s SYMMETRICAL OUTPUT IMPEDANCE: |IOH|=IOL = 8 mA (MIN) s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573 s IMPROVED LATCH-UP IMMUNITY s LOW NOISE: VOLP = 0.9V (Max.) DESCRIPTION The 74VHCT573A is an advanced high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C 2MOS technology. This 8 bit D-Type latch is controlled by a latch enable input (LE) and an output enable input (OE). While the LE input is held at a high level, the Q outputs will follow the data inputs precisely. When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS ® SOP TSSOP ORDER CODES PACKAGE T UBE T & R SOP 74VHCT573AM 74VHCT573AMTR TSSOP 74VHCT573ATTR 1/10 |
Аналогичный номер детали - 74VHCT573ATTR |
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Аналогичное описание - 74VHCT573ATTR |
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