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TMP320C6415CZLZA300 датащи(PDF) 2 Page - Texas Instruments

номер детали TMP320C6415CZLZA300
подробное описание детали  FIXED-POINT DIGITAL SIGNAL PROCESSORS
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TMP320C6415CZLZA300 датащи(HTML) 2 Page - Texas Instruments

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TMS320C6414, TMS320C6415, TMS320C6416
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS146L − FEBRUARY 2001 − REVISED JULY 2004
2
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
Table of Contents
reset
78
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
absolute maximum ratings over operating case
temperature range
79
. . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions
79
. . . . . . . . . . . . . . . .
electrical characteristics over recommended ranges of
supply voltage and operating case temperature
80
.
recommended clock and control signal transition
behavior
80
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
parameter measurement information
81
. . . . . . . . . . . . . . .
input and output clocks
83
. . . . . . . . . . . . . . . . . . . . . . . . . . .
asynchronous memory timing
87
. . . . . . . . . . . . . . . . . . . . .
programmable synchronous interface timing
91
. . . . . . . .
synchronous DRAM timing
96
. . . . . . . . . . . . . . . . . . . . . . . .
HOLD/HOLDA timing
106
. . . . . . . . . . . . . . . . . . . . . . . . . . .
BUSREQ timing
107
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
reset timing
108
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
external interrupt timing
110
. . . . . . . . . . . . . . . . . . . . . . . . .
host-port interface (HPI) timing
111
. . . . . . . . . . . . . . . . . . . .
peripheral component interconnect (PCI) timing
[C6415 and C6416 only]
116
. . . . . . . . . . . . . . . . . . . .
multichannel buffered serial port (McBSP) timing
119
. . . .
UTOPIA slave timing [C6415 and C6416 only]
130
. . . . . .
timer timing
133
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
general-purpose input/output (GPIO) port timing
134
. . . .
JTAG test-port timing
135
. . . . . . . . . . . . . . . . . . . . . . . . . . .
mechanical data
136
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
revision history
2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GLZ and ZLZ BGA packages (bottom view)
6
. . . . . . . . . . . . .
description
7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
device characteristics
8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
device compatibility
9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
functional block and CPU (DSP core) diagram
10
. . . . . . . . . .
CPU (DSP core) description
11
. . . . . . . . . . . . . . . . . . . . . . . . .
memory map summary
14
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
peripheral register descriptions
17
. . . . . . . . . . . . . . . . . . . . . . .
EDMA channel synchronization events
30
. . . . . . . . . . . . . . . .
interrupt sources and interrupt selector
32
. . . . . . . . . . . . . . . .
signal groups description
34
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
device configurations
39
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
multiplexed pins
43
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
debugging considerations
43
. . . . . . . . . . . . . . . . . . . . . . . . . . .
terminal functions
45
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
development support
65
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
device support
66
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
clock PLL
69
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
general-purpose input/output (GPIO)
72
. . . . . . . . . . . . . . . . . .
power-down mode logic
73
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
power-supply sequencing
75
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
power-supply decoupling
76
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
IEEE 1149.1 JTAG compatibility statement
77
. . . . . . . . . . . . .
EMIF device speed
77
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
bootmode
78
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
REVISION HISTORY
This data sheet revision history highlights the technical changes made to the SPRS146K device-specific data
sheet to make it an SPRS146L revision.
Scope: Applicable updates to the C64x device family, specifically relating to the C6414, C6415, and C6416
devices, have been incorporated. Added C6414, C6415, and C6416 silicon revision 2.0 devices and associated
device-specific information at the production data (PD) stage of development.
The extended temperature devices for silicon revision 2.0 (C641x A-5E0, C641xA-6E3) are at the advance infor-
mation (AI) stage of development. All other devices are at the Production Data (PD) stage of development.
PAGE(S)
NO.
ADDITIONS/CHANGES/DELETIONS
1
Features:
Changed the Viterbi Decoder Coprocessor (VCP) [C6416] sub-bullet from “Supports Over 500 7.95-Kbps AMR” to
“Supports Over 600 7.95-Kbps AMR”
Changed the Turbo Decoder Coprocessor (TCP) [C6416] sub-bullet from “Supports up to Six 2-Mbps 3GPP (6 Iterations)”
to “Supports up to 7 2-Mbps or 43 384-Kbps 3GPP (6 Iterations)”
7
Description section:
“With performance of up to 5760 million instructions per second (MIPS) ...” paragraph
Changed “The C64x can produce four 32-bit multiply-accumulates (MACs) per ...” sentence to “The C64x can produce four
16-bit multiply-accumulates (MACs) per ...”


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