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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMP320C6415DGLZA5E0 датащи(PDF) 88 Page - Texas Instruments |
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TMP320C6415DGLZA5E0 датащи(HTML) 88 Page - Texas Instruments |
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88 / 139 page  TMS320C6414, TMS320C6415, TMS320C6416 FIXEDPOINT DIGITAL SIGNAL PROCESSORS SPRS146L − FEBRUARY 2001 − REVISED JULY 2004 88 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 ASYNCHRONOUS MEMORY TIMING (CONTINUED) timing requirements for asynchronous memory cycles for EMIFB module†‡§ (see Figure 22 and Figure 23) NO. −5E0 −6E3 −7E3 A−5E0 A−6E3 UNIT MIN MAX MIN MAX 3 tsu(EDV-AREH) Setup time, EDx valid before ARE high 6.2 6.2 ns 4 th(AREH-EDV) Hold time, EDx valid after ARE high 1 1 ns 6 tsu(ARDY-EKO1H) Setup time, ARDY valid before ECLKOUTx high 3 3 ns 7 th(EKO1H-ARDY) Hold time, ARDY valid after ECLKOUTx high Rev 1.1 and earlier 1.2 1.7 ns 7 th(EKO1H-ARDY) Hold time, ARDY valid after ECLKOUTx high Rev 2.0 1.3 1.7 ns † To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is only recognized two cycles before the end of the programmed strobe time and while ARDY is low, the strobe time is extended cycle-by-cycle. When ARDY is recognized low, the end of the strobe time is two cycles after ARDY is recognized high. To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met. ‡ RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. § These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the asynchronous memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and BAWE (for EMIFB)]. switching characteristics over recommended operating conditions for asynchronous memory cycles for EMIFB module‡§¶# (see Figure 22 and Figure 23) NO. PARAMETER −5E0, A−5E0, −6E3, A−6E3, −7E3 UNIT MIN MAX 1 tosu(SELV-AREL) Output setup time, select signals valid to ARE low RS * E − 1.6 ns 2 toh(AREH-SELIV) Output hold time, ARE high to select signals invalid RH * E − 1.7 ns 5 td(EKO1H-AREV) Delay time, ECLKOUTx high to ARE valid 0.8 6.6 ns 8 tosu(SELV-AWEL) Output setup time, select signals valid to AWE low WS * E − 1.9 ns 9 toh(AWEH-SELIV) Output hold time, AWE high to select signals invalid WH * E − 1.7 ns 10 td(EKO1H-AWEV) Delay time, ECLKOUTx high to AWE valid 0.9 6.7 ns ‡ RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. § These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the asynchronous memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and BAWE (for EMIFB)]. ¶ E = ECLKOUT1 period in ns for EMIFA or EMIFB # Select signals for EMIFA include: ACEx, ABE[7:0], AEA[22:3], AAOE; and for EMIFA writes, include AED[63:0]. Select signals EMIFB include: BCEx, BBE[1:0], BEA[20:1], BAOE; and for EMIFB writes, include BED[15:0]. |
Аналогичный номер детали - TMP320C6415DGLZA5E0 |
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Аналогичное описание - TMP320C6415DGLZA5E0 |
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