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SL15100ZIT-XXX датащи(PDF) 11 Page - SpectraLinear Inc

номер детали SL15100ZIT-XXX
подробное описание детали  Prigrammable Spread Spectrum Clock Generator (SSCG)
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производитель  SPECTRALINEAR [SpectraLinear Inc]
домашняя страница  http://www.spectralinear.com
Logo SPECTRALINEAR - SpectraLinear Inc

SL15100ZIT-XXX датащи(HTML) 11 Page - SpectraLinear Inc

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Rev 1.8, August 10, 2007
Page 11 of 16
SL15100
Operating Supply Current
IDD
FIN=30MHz, REFCLK=30MHz
SSCLK=66MHz, PD#/OE=VDD
SSON#=GND, CL=0
-
7.0
8.4
mA
Standby Current
ISBC
PD#=GND
-
80
100
A
Output Leakage Current
IOL
Pins 6 and 7
-10
-
10
A
Minimum setting value
-
8.5
-
pF
Maximum setting value
-
40
-
pF
Programmable
Input Capacitance at
Pins 2 and 3
CXIN
CXOUT
Resolution (programming steps)
-
0.5
-
pF
Input Capacitance
CIN2
Pins 4 and 8
-
4
7
pF
Load Capacitance
CL
SSCLK/REFCLK , Pins 6 and 7
-
-
15
pF
AC Electrical Characteristics (I-Grade)
Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85 Deg C
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Input Frequency Range
FIN1
Crystal or Ceramic Resonator
8
-
48
MHz
Input Frequency Range
FIN2
External Clock
8
-
166
MHz
Output Frequency Range FOUT1
SSCLK
3
-
200
MHz
Output Frequency Range FOUT2
REFCLK, crystal or resonator input
0.25
-
48
MHz
Output Frequency Range FOUT3
REFCLK, clock input
0.25
-
166
MHz
Output Duty Cycle
DC1
SSCLK
45
50
55
%
Output Duty Cycle
DC2
REFCLK
45
50
55
%
Input Duty Cycle
DCIN
Clock Input, Pin 3
40
50
60
%
Output Rise/Fall Time
tr/f1
Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD
-
4.80
5.80
ns
Output Rise/Fall Time
tr/f2
Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD
-
2.60
3.10
ns
Output Rise/Fall Time
tr/f3
Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD
-
1.80
2.20
ns
Output Rise/Fall Time
tr/f4
Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD
-
1.40
1.70
ns
Output Rise/Fall Time
tr/f5
Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD
-
1.10
1.35
ns
Output Rise/Fall Time
tr/f6
Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD
-
0.90
1.10
ns
Output Rise/Fall Time
tr/f7
Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD
-
0.70
0.85
ns
Cycle-to-Cycle Jitter
(SSCLK – Pin 7)
CCJ1
CLKIN=SSCLK=166MHz, 2%Spread
REFCLK=Off
-
115
150
ps


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