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LM3224MM-ADJ датащи(PDF) 11 Page - National Semiconductor (TI) |
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LM3224MM-ADJ датащи(HTML) 11 Page - National Semiconductor (TI) |
11 / 18 page Operation (Continued) must exceed the switch current limit. Using Schottky diodes with lower forward voltage drop will decrease power dissipa- tion and increase efficiency. DC GAIN AND OPEN-LOOP GAIN Since the control stage of the converter forms a complete feedback loop with the power components, it forms a closed- loop system that must be stabilized to avoid positive feed- back and instability. A value for open-loop DC gain will be required, from which you can calculate, or place, poles and zeros to determine the crossover frequency and the phase margin. A high phase margin (greater than 45˚) is desired for the best stability and transient response. For the purpose of stabilizing the LM3224, choosing a crossover point well be- low where the right half plane zero is located will ensure sufficient phase margin. To ensure a bandwidth of 1⁄2 or less of the frequency of the RHP zero, calculate the open-loop DC gain, A DC. After this value is known, you can calculate the crossover visually by placing a −20dB/decade slope at each pole, and a +20dB/ decade slope for each zero. The point at which the gain plot crosses unity gain, or 0dB, is the crossover frequency. If the crossover frequency is less than 1⁄2 the RHP zero, the phase margin should be high enough for stability. The phase mar- gin can also be improved by adding C C2 as discussed later in this section. The equation for A DC is given below with addi- tional equations required for the calculation: mc ) 0.072fs (in V/s) where R L is the minimum load resistance, VIN is the mini- mum input voltage, g m is the error amplifier transconduc- tance found in the Electrical Characteristics table, and R D- SON is the value chosen from the graph "NMOS R DSON vs. Input Voltage" in the Typical Performance Characteristics section. INPUT AND OUTPUT CAPACITOR SELECTION The switching action of a boost regulator causes a triangular voltage waveform at the input. A capacitor is required to reduce the input ripple and noise for proper operation of the regulator. The size used is dependant on the application and board layout. If the regulator will be loaded uniformly, with very little load changes, and at lower current outputs, the input capacitor size can often be reduced. The size can also be reduced if the input of the regulator is very close to the source output. The size will generally need to be larger for applications where the regulator is supplying nearly the maximum rated output or if large load steps are expected. A minimum value of 10µF should be used for the less stressful condtions while a 22µF to 47µF capacitor may be required for higher power and dynamic loads. Larger values and/or lower ESR may be needed if the application requires very low ripple on the input source voltage. The choice of output capacitors is also somewhat arbitrary and depends on the design requirements for output voltage ripple. It is recommended that low ESR (Equivalent Series Resistance, denoted R ESR) capacitors be used such as ceramic, polymer electrolytic, or low ESR tantalum. Higher ESR capacitors may be used but will require more compen- sation which will be explained later on in the section. The ESR is also important because it determines the peak to peak output voltage ripple according to the approximate equation: ∆V OUT ) 2 ∆i LRESR (in Volts) A minimum value of 10µF is recommended and may be increased to a larger value. After choosing the output capaci- tor you can determine a pole-zero pair introduced into the control loop by the following equations: Where R L is the minimum load resistance corresponding to the maximum load current. The zero created by the ESR of the output capacitor is generally very high frequency if the ESR is small. If low ESR capacitors are used it can be neglected. If higher ESR capacitors are used see the High Output Capacitor ESR Compensation section. Some suit- able capacitor vendors include Vishay, Taiyo-Yuden, and TDK. RIGHT HALF PLANE ZERO A current mode control boost regulator has an inherent right half plane zero (RHP zero). This zero has the effect of a zero in the gain plot, causing an imposed +20dB/decade on the rolloff, but has the effect of a pole in the phase, subtracting another 90˚ in the phase plot. This can cause undesirable effects if the control loop is influenced by this zero. To ensure the RHP zero does not cause instability issues, the control loop should be designed to have a bandwidth of less than 1⁄2 the frequency of the RHP zero. This zero occurs at a fre- quency of: where I LOAD is the maximum load current. SELECTING THE COMPENSATION COMPONENTS The first step in selecting the compensation components R C and C C is to set a dominant low frequency pole in the control loop. Simply choose values for R C and CC within the ranges given in the Introduction to Compensation section to set this pole in the area of 10Hz to 500Hz. The frequency of the pole created is determined by the equation: www.national.com 11 |
Аналогичный номер детали - LM3224MM-ADJ |
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Аналогичное описание - LM3224MM-ADJ |
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