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L6382D5 датащи(PDF) 5 Page - STMicroelectronics

номер детали L6382D5
подробное описание детали  Power management unit for microcontrolled ballast
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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L6382D5
Pin settings
5/21
9LSG
Low Side Driver Output. This pin must be connected to the gate of the half-
bridge low side power MOSFET. A resistor connected between this pin and the
power MOS gate can be used to reduce the peak current.
An internal 20K
Ω resistor toward ground avoids spurious and undesired
MOSFET turn-on.
The totem pole output stage is able to drive power with a peak current of
120mA source and 120mA sink.
10
Vcc
Supply Voltage for the signal part of the IC and for the drivers.
11
BOOT
High-side gate-drive floating supply Voltage. The bootstrap capacitor
connected between this pin and pin 13 (OUT) is fed by an internal
synchronous bootstrap diode driven in phase with the low-side gate-drive. This
patented structure normally replaces the external diode.
12
HSG
High Side Driver Output. This pin must be connected to the gate of the half
bridge high side power MOSFET . A resistor connected between this pin and
the power MOS gate can be used to reduce the peak current.
An internal 20K
Ω resistor toward OUT pin avoids spurious and undesired
MOSFET turn-on
The totem pole output stage is able to drive the power MOS with a peak
current of 120mA source and 120mA sink.
13
OUT
High-side gate-drive floating ground. Current return for the high-side gate-drive
current. Layout carefully the connection of this pin to avoid too large spikes
below ground.
14
N.C.
Not connected
15
HVSU
High-voltage start-up. The current flowing into this pin charges the capacitor
connected between pin Vcc and GND to start up the IC. Whilst the chip is in
save mode, the generator is cycled on-off between turn-on and save mode
voltages. When the chip works in operating mode the generator is shut down
and it is re-enabled when the Vcc voltage falls below the UVLO threshold.
According to the required VREF pin current, this pin can be connected to the
rectified mains voltage either directly or through a resistor.
16
N.C.
High-voltage spacer. The pin is not connected internally to isolate the high-
voltage pin and comply with safety regulations (creepage distance) on the
PCB.
17
HEG
Output for the HEI block; this driver can be used to drive the MOS employed in
isolated filaments preheating. An internal 20K
Ω resistor toward ground avoids
spurious and undesired MOSFET turn-on.
18
CSO
Output of current sense comparator, compatible with 5V CMOS logic; during
operating mode, the pin is forced low whereas whenever the OC comparator is
triggered (CSI> 0.55 typ.) the pin latches high.
19
CSI
Input of current sense comparator, it is enabled only during operating mode;
when the pin voltage exceeds the internal threshold, the CSO pin is forced
high and the half bridge drivers are disabled. It exits from this condition by
either cycling the Vcc below the UVLO or with LGI=HGI=low simultaneously.
20
VREF
Voltage reference. During operating mode an internal generator provides an
accurate voltage reference that can be used to supply up to 30mA to an
external circuit. A small film capacitor (0.22
µF min.), connected between this
pin and GND is recommended to ensure the stability of the generator and to
prevent noise from affecting the reference.
Table 1. Pin description (continued)
Name
Pin N°
Description


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